5 FN7863.0 November 1, 2011 thDO Output Data Remains Valid After DCLOCK ↓ CLOAD = 100" />
參數(shù)資料
型號： ISL2671286IBZ
廠商： Intersil
文件頁數(shù)： 11/15頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SPI/SRL 20K 8SOIC
標(biāo)準(zhǔn)包裝： 980
位數(shù)： 12
采樣率（每秒）： 20k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.4mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 管件
輸入數(shù)目和類型： 1 個偽差分，單極
ISL2671286
5
FN7863.0
November 1, 2011
thDO
Output Data Remains Valid After DCLOCK
↓
CLOAD = 100pF
15
30
ns
tf
DOUT Fall Time
See test circuits; Figure 4
1
100
ns
tR
DOUT Rise Time
See test circuits; Figure 4
1
100
ns
tCSD
Delay Time, CS/SHDN
↓ to DCLOCK↓
See operating sequence; Figure 3
0
ns
tSUCS
Delay Time, CS/SHDN
↓ to DCLOCK↑
See operating sequence; Figure 3
30
ns
NOTE:
11. During characterization, tDIS is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the ADS1286
loading (3k, 100pF) is calculated.
Timing Specifications At fCLK = 200kHz , unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
tSUCS
B10
B9B8B7B6B5B4B3B2
B1B0
B11
B10
B9B8
Null
Bit
Hi-Z
Null
Bit
CS/SHDN
DCLOCK
DOUT
tCSD
tCYC
POWER
DOWN
tSMPL
tCONV
tDATA
Note: (1) After completing the data transfer, additional clocks applied while CS/SHDN is low
will result in the previous data being retransmitted LSB-first, followed by indefinite
transmission of zeros
tSUCS
B10
B9B8B7B6B5B4B3B2
B1B0
B11
B10
B9
B8
Null
Bit
Hi-Z
CS/SHDN
DCLOCK
DOUT
tCSD
tCYC
POWER
DOWN
tSMPL
tCONV
tDATA
Note: (2) After completing the data transfer, additional clocks applied while CS/SHDN is low
will result in indefinite transmission of zeros
B1
B2
B3
B4
B5
B7
B6
B11
(MSB)
B11
(MSB)
(1)
(2)
FIGURE 4. EQUIVALENT LOAD CIRCUIT
OUTPUT PIN
CL
10pF
+VCC
2.85k
RL
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