4 FN7863.0 November 1, 2011 REFERENCE INPUT REF REF Input Range 1.25 2.5 VCC + 0.05 V REFLEAK Current Drain CS/SHDN = VCC -2.5 0.01 " />
參數(shù)資料
型號(hào)： ISL2671286IBZ
廠商： Intersil
文件頁(yè)數(shù)： 10/15頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SPI/SRL 20K 8SOIC
標(biāo)準(zhǔn)包裝： 980
位數(shù)： 12
采樣率（每秒）： 20k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.4mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)偽差分，單極
ISL2671286
4
FN7863.0
November 1, 2011
REFERENCE INPUT
REF
REF Input Range
1.25
2.5
VCC + 0.05
V
REFLEAK
Current Drain
CS/SHDN = VCC
-2.5
0.01
2.5
A
tCYC ≥ 640s, fCLK ≤ 25kHz
0.06
20
A
tCYC = 80s, fCLK= 200kHz
0.5
20
A
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
VIH
Input High Voltage
3+VCC
V
VIL
Input Low Voltage
0.0
0.8
V
VOH
Output High Voltage
IOH = 250A
3+VCC
V
VOL
Output Low Voltage
IOL = 250A
0.0
0.4
V
Data Format
Straight Binary
ILEAK
Input DC Leakage Current
-1
0.01
1
A
CIN
Input Capacitance
9pF
IOZ
Floating-State Output Leakage
Current
-1
0.01
1
A
COUT
Floating-State Output Capacitance
6
pF
POWER SUPPLY REQUIREMENTS
+VCC
Power Supply Voltage
4.50
5
5.25
V
VANA
Quiescent Current
tCYC ≥ 640s, fCLK ≤ 25kHz
280
500
A
tCYC = 90s, fCLK= 200kHz
360
600
A
Power Down
CS/SHDN = VCC
0.5
3
A
TEMPERATURE RANGE
Specified Performance
-40
+85
°C
NOTES:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. The absolute voltage applied to each analog input must be between GND and +VCC to guarantee datasheet performance.
10. Applies only to +IN.
Electrical Specifications +VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK =16 fSAMPLE , unless otherwise noted. Typical
values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
Timing Specifications At fCLK = 200kHz , unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
tSMPL
Analog Input Sample Time
See operating sequence; Figure 3
1.5
2.0
CLK
Cycles
tSMPL (MAX) Maximum Sampling Frequency
20
kHz
tCONV
Conversion Time
See operating sequence; Figure 3
12
CLK
Cycles
tdDO
Delay Time, DCLOCK
↓ to DOUT Data Valid
See test circuits; Figure 4
36
150
ns
tDIS
Delay Time, CS/SHDN
↑ to DOUT Hi-Z
See test circuits; Figure 4 (Note 11)
50
ns
tEN
Delay Time, DCLOCK
↓ to DOUT Enable
See test circuits; Figure 4
21
100
ns
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