20 FN6954.1 September 9, 2011 PCB Board Layout and System Configuration The ISL26132,ISL26134 ADC is a very low noise conver" />
參數(shù)資料
型號(hào)： ISL26134AVZ
廠商： Intersil
文件頁(yè)數(shù)： 13/23頁(yè)
文件大小： 0K
描述： IC ADC 24BIT SRL 80SPS 28TSSOP
標(biāo)準(zhǔn)包裝： 500
位數(shù)： 24
采樣率（每秒）： 80
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 80mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類型： 4 個(gè)差分，雙極
ISL26132, ISL26134
20
FN6954.1
September 9, 2011
PCB Board Layout and System
Configuration
The ISL26132,ISL26134 ADC is a very low noise converter. To
achieve the full performance available from the device will
require attention to the printed circuit layout of the circuit board.
Care should be taken to have a full ground plane without
impairments (traces running through it) directly under the chip
on the back side of the circuit board. The analog input signals
should be laid down adjacent (AIN+ and AIN- for each channel) to
achieve good differential signal practice and routed away from
any traces carrying active digital signals. The connections from
the CAP pins to the off-chip filter capacitor should be short, and
without any digital signals nearby. The crystal, if used should be
connected with relatively short leads. No active digital signals
should be routed near or under the crystal case or near the
traces, which connect it to the ADC. The AGND and DGND pins of
the ADC should be connected to a common solid ground plane.
All digital signals to the chip should be powered from the same
supply, as that used for DVDD (do not allow digital signals to be
active high unless the DVDD supply to the chip is alive). Route all
active digital signals in a way to keep distance from any analog
pin on the device (AIN, VREF, CAP, AVDD). Power on the AVDD
supply should be active before the VREF voltage is present.
PCB layout patterns for the chips (ISL26132 and ISL26134) are
found on the respective package outline drawings on pages 22,
and 23.
AVDD
VREF+
AIN+1
AIN-1
AIN+2
AIN-2
VREF-
AGND
DGND
TEMP
A0
SPEED
XTALOUT
PDWN
SCLK
SDO/RDY
GAIN0
GAIN1
DVDD
XTALIN/CLOCK
MICRO
CONTROLLER
16
11
12
14
13
15
17
2, 5, 6
7
8
21
3
4
22
23
24
19
20
+3V
+5V
0.1F
18
1
FIGURE 39. THERMOCOUPLE MEASUREMENT APPLICATION
4.9152
MHz
ISL21009
4.096V
10nF
1F
10k
0.1F
TYPE K
5M
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