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參數(shù)資料
| 型號： | ISL24212IRTZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROG 8BIT VCOM CALIBRTR 10TDF |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 類型： | 校準(zhǔn)器 |
| 應(yīng)用： | LCD 驅(qū)動(dòng)器，基準(zhǔn)電壓發(fā)生器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-TDFN（3x3） |
| 包裝： | 管件 |
ISL24212
8
FN7590.0
March 15, 2011
span of VCOM can be found:
Assuming that the IDVROUT(MIN) = 0 instead of ISTEP, the
expression in Equation 14 simplifies to:
DVR_OUT Pin Leakage Current
When the voltage on the DVR_OUT pin is greater than 10V, an
additional leakage current flows into the pin in addition to the
pin current for DVR_OUT pin voltage up to 19V. In applications
where the voltage on the DVR_OUT pin will be greater than 10V,
the actual output voltage will be lower than the voltage
calculated by Equation 8 due to this extra current. The graph in
Power Supply Sequence
The recommended power supply sequencing is shown in
at the same time as AVDD. The minimum time for tVS is 0s.
When removing power, the sequence of VDD and AVDD is not
important.
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed, may result in
corrupted data in the EEPROM.
Operating and Programming
Supply Voltage and Current
To program the EEPROM, AVDD must be ≥10.8V. If further
programming is not required, the ISL24212 will operate over an
AVDD range of 4.5V to 19V.
During EEPROM programming, IDD and IAVDD will temporarily be
4-5x higher for up to 100ms (tPROG).
Up/Down Counter Interface
The ISL24212 allows the adjustment of the output VCOM voltage
and the programming of the non-volatile memory through a
single pin (CTL) when the CE (counter enable) pin is high. The CTL
pin is biased so that its voltage is set to VDD/2 if the driving
circuit is set to Tristate or High Impedance (Hi-Z), allowing
up/down operation using common digital I/O logic.
CTL Pin
When a mid-high-mid transition is detected on the CTL pin (see
Figure 11), the internal register value counts down by one at the
trailing (high-mid) edge, and the output VCOM voltage is
increased according to Equation 8. Similarly, when a mid-low-mid
transition is detected on the CTL pin, the internal register value
counts up by one at the trailing (low-mid) edge, and the output
VCOM voltage is decreased. Once the maximum or minimum
value is reached, the counter saturates and will not overflow or
underflow beyond those values.
CTL should have a noise filter to reduce bouncing or noise on the
input that could cause unwanted counts when the CE pin is high.
Figure 8 shows a simple debouncing circuit consisting of a series
1k
Ω resistor and a shunt 0.01F capacitor connected on the CTL
pin. To avoid unintentional adjustment, the ISL24212 guarantees
to reject CTL pulses shorter than 20s.
This pin is pulled above 4.9V to program the EEPROM. See
“Programming the EEPROM” on page 9 for details.
After CE (Counter Enable) is asserted and after programming
EEPROM, the very first CTL pulse is ignored (see Figure 11) to
avoid the possibility of a false count (CTL state may be unknown
after programming).
VCOMSPAN
AVDD
R2
R1 R2
+
--------------------
1
256
----------
–
R1
20RSET
--------------------
=
(EQ. 14)
VCOMSPAN
R1 R
2
R1 R2
+
--------------------
AVDD
20RSET
R1 R
2
R1 R2
+
--------------------
IDVROUT MAX
()
==
(EQ. 15)
FIGURE 6. DVR_OUT PIN LEAKAGE CURRENT
02468
10
12
14
16
18
20
OUT PIN VOLTAGE (V)
CU
RRE
N
T
(mA
)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
OUT PIN CURRENT
SET PIN CURRENT
REGISTER = 255
VDD
AVDD
tVS
FIGURE 7. POWER SUPPLY SEQUENCE
FIGURE 8. EXTERNAL DEBOUNCER ON CTL PIN
ISL24212
CTL
0.01F
1k
Ω
AVDD
CLOSE TO
EEPROM
PROGRAM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL24212IRTZ-EVALZ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable VCOM Calibrator with EEPROM and Output Buffer |
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