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參數(shù)資料
| 型號： | ISL1209IU10-TK |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | Low Power RTC with Battery Backed SRAM and Event Detection |
| 中文描述： | REAL TIME CLOCK, PDSO8 |
| 封裝： | PLASTIC, MO-187BA, MSOP-8 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 416K |
| 代理商： | ISL1209IU10-TK |
4
FN6109.1
September 27, 2005
I
2
C Interface Specifications
Test Conditions:V
DD
= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 4)
MAX
UNITS
V
IL
SDA and SCL input buffer LOW
voltage
-0.3
0.3 x
V
DD
V
V
IH
SDA and SCL input buffer HIGH
voltage
0.7 x
V
DD
V
DD
+
0.3
V
Hysteresis
SDA and SCL input buffer hysteresis
0.05 x
V
DD
V
V
OL
SDA output buffer LOW voltage,
sinking 3mA
V
DD
= 5V, I
OL
= 3mA
0.4
V
Cpin
SDA and SCL pin capacitance
T
A
= 25°C, f = 1MHz, V
DD
= 5V, V
IN
= 0V,
V
OUT
= 0V
10
pF
f
SCL
SCL frequency
400
kHz
t
IN
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
t
AA
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of V
DD
, until SDA
exits the 30% to 70% of V
DD
window.
900
ns
t
BUF
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of V
DD
during a STOP
condition, to SDA crossing 70% of V
DD
during
the following START condition.
1300
ns
t
LOW
Clock LOW time
Measured at the 30% of V
DD
crossing.
1300
ns
t
HIGH
Clock HIGH time
Measured at the 70% of V
DD
crossing.
600
ns
t
SU:STA
START condition setup time
SCL rising edge to SDA falling edge. Both
crossing 70% of V
DD
.
600
ns
t
HD:STA
START condition hold time
From SDA falling edge crossing 30% of V
DD
to
SCL falling edge crossing 70% of V
DD
.
600
ns
t
SU:DAT
Input data setup time
From SDA exiting the 30% to 70% of V
DD
window, to SCL rising edge crossing 30% of
V
DD.
100
ns
t
HD:DAT
Input data hold time
From SCL falling edge crossing 30% of V
DD
to
SDA entering the 30% to 70% of V
DD
window.
0
900
ns
t
SU:STO
STOP condition setup time
From SCL rising edge crossing 70% of V
DD
, to
SDA rising edge crossing 30% of V
DD
.
600
ns
t
HD:STO
STOP condition hold time
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
DD
.
600
ns
t
DH
Output data hold time
From SCL falling edge crossing 30% of V
DD
,
until SDA enters the 30% to 70% of V
DD
window.
0
ns
t
R
SDA and SCL rise time
From 30% to 70% of V
DD.
20 +
0.1 x Cb
300
ns
t
F
SDA and SCL fall time
From 70% to 30% of V
DD.
20 +
0.1 x Cb
300
ns
Cb
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL bus pull-up resistor off-
chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k
.
For Cb = 40pF, max is about 15~20k
1
k
NOTES:
1. IRQ & F
OUT
and EVDET Inactive.
2. LPMODE = 0 (default).
3. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
4. Typical values are for T = 25°C and 3.3V supply voltage.
5. V
SUP
=V
DD
if in V
DD
Mode, V
SUP
=V
BAT
if in V
BAT
Mode.
ISL1209
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