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參數(shù)資料
| 型號： | ISL12032IVZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 14TSSOP |
| 產(chǎn)品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 1 |
| 類型： | 時間事件記錄器 |
| 特點： | 警報器，SRAM，涓流充電器 |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS:hh（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1246 (CN2011-ZH PDF) |
| 其它名稱： | ISL12032IVZ-TDKR |
17
FN6618.3
May 5, 2011
Where the ROUT is the selected resistor between VDD and
and VBAT = 3.0V. Note that the resistor value changes with
VDD input voltage and VBAT voltage, as well as with
temperature.
Power Supply Control Register (PWRVDD)
CLEAR TIME STAMP BIT (CLRTS)
This bit clears both the Time Stamp VDD to Battery (TSV2B)
and Time Stamp Battery to VDD (TSB2V) sections. The
default setting is “0” which allows normal operation. Setting
CLRTS = 1 performs the clear timestamp register function at
the conclusion of a successful write operation.
I2C IN BATTERY MODE (I2CBAT)
This bit allows I2C operation in battery backup mode (VBAT
powered) when set to “1”. When reset to “0”, the I2C
operation is disabled in battery mode, which results in the
lowest IDD current.
Note that when the I2C operation is desired in VBAT mode,
the SCL and SDA pull-ups must go to the VBAT source for
proper communications. This will result in additional VBAT
current drain (on top of the increased device VBAT current)
during serial communications.
VDD BROWNOUT TRIP VOLTAGE (VDDTRIP <2:0>)
These bits set the 6 trip levels for the VDD alarm and VBAT
switchover. The LVDD bit in the SRDC is set to “1” when
Battery Voltage Warning Register (PWRVBAT)
This register controls the trip points for the two VBAT
warnings, with levels set to approximately 85% and 75% of
the nominal battery level.
VBAT HYSTERESIS (BHYS)
This bit enables/disables the hysteresis voltage for the
VDD/VBAT switchover. When set to “1”, hysteresis is enabled
and switching to VBAT occurs at approximately 50mV below
the VDD Trip point (set by VDDTrip<2:0>). Switching from
VBAT to VDD power will occur at approximately 50mV above
the VDD trip point.
When set to “0”, there is no hysteresis and switchover will
occur at exactly the VDD trip point. Note that for slow moving
VDD power-down and power-up signals there can be some
extra switching cycles without hysteresis.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>)
Three bits selects the first alarm (85% of Nominal VBAT) level
for the battery voltage monitor. There are total of 7 levels that
could be selected for the first warning. Any of the levels could
be selected as the first warning with no reference as to nominal
VBAT voltage level. See Table 18 for typical values.
TABLE 14. RESISTOR SELECTION REGISTER
TRKRO1
TRKRO0
Rtrk
UNITS
0
1300
Ω
0
1
2200
Ω
1
0
3600
Ω
1
7800
Ω
TABLE 15. POWER SUPPLY CONTROL REGISTER (PWRVDD)
ADDR
7
6
5
4
3
2
1
0
11h
CLRTS
X
I2CBAT
LVENB
X
VDD
Trip2
VDD
Trip1
VDD
Trip0
TABLE 16. VDD TRIP LEVELS
VDDTrip2
VDDTrip1
VDDTrip0
TRIP
VOLTAGE
(V)
0
2.295
0
1
2.550
0
1
0
2.805
I
MAX
V
DD
V
BAT
–
R
OUT
---------------------------------
=
(EQ. 1)
0
1
3.060
1
0
4.250
1
0
1
4.675
TABLE 17. BATTERY VOLTAGE WARNING REGISTER
(PWRVBAT)
ADDR
7
6
5
4
3
2
1
0
12h
X BHYS VB85T
p2
VB85T
p1
VB85T
p0
VB75T
p2
VB75T
p1
VB75T
p0
TABLE 16. VDD TRIP LEVELS
VDDTrip2
VDDTrip1
VDDTrip0
TRIP
VOLTAGE
(V)
ISL12032
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