參數(shù)資料
型號: ISL12032IVZ-T
廠商: Intersil
文件頁數(shù): 15/26頁
文件大小: 0K
描述: IC RTC LP BATT BACK SRAM 14TSSOP
產(chǎn)品培訓模塊: Solutions for Industrial Control Applications
標準包裝: 1
類型: 時間事件記錄器
特點: 警報器,SRAM,涓流充電器
存儲容量: 128B
時間格式: HH:MM:SS:hh(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 14-TSSOP
包裝: 標準包裝
產(chǎn)品目錄頁面: 1246 (CN2011-ZH PDF)
其它名稱: ISL12032IVZ-TDKR
22
FN6618.3
May 5, 2011
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 6). On power-up of the ISL12032, the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12032 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 6). A START condition is ignored during the power-up
sequence.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 6). A STOP condition at the end of
a read operation or at the end of a write operation to memory
only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 7).
The ISL12032 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12032 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
FIGURE 6. VALID DATA CHANGES, START AND STOP CONDITIONS
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 8. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL12032
A
C
K
10
0
11
A
C
K
WRITE
SIGNAL AT SDA
00 00
11 1
ADDRESS
BYTE
ISL12032
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