6 FN6668.9 June 20, 2012 OSCILLATOR ACCURACY ΔFoutI Oscillator Initial Accuracy
參數(shù)資料
型號(hào)： ISL12022MIBZ-T
廠商： Intersil
文件頁(yè)數(shù)： 28/31頁(yè)
文件大?。?/td> 0K
描述： IC RTC/CALENDAR TEMP SENS 20SOIC
應(yīng)用說(shuō)明： Addressing Power Issues in Real Time Clock Appls
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，夏令時(shí)，閏年，SRAM
存儲(chǔ)容量： 128B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ISL12022MIBZ-TDKR
ISL12022M
6
FN6668.9
June 20, 2012
OSCILLATOR ACCURACY
ΔFoutI
Oscillator Initial Accuracy
VDD = 3.3V
-2
+8
ppm
ΔFoutR
Oscillator Accuracy after Reflow Cycle
VDD = 3.3V
±5
ppm
ΔFoutT
Oscillator Stability vs Temperature
VDD = 3.3V
±2
ppm
ΔFoutV
Oscillator Stability vs Voltage
2.7V
≤ VDD ≤ 5.5V
-3
+3
ppm
Temp
Temperature Sensor Accuracy
VDD = VBAT = 3.3V
±2
°C
IRQ/FOUT (OPEN DRAIN OUTPUT)
VOL
Output Low Voltage
VDD = 5V, IOL = 3mA
0.4
V
VDD = 2.7V, IOL = 1mA
0.4
V
DC Operating Characteristics RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 7)
TYP
(Note 8)
MAX
(Note 7)
UNITS
NOTES
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 7)
TYP
(Note 8)
MAX
(Note 7)
UNITS
NOTES
VDDSR-
VDD Negative Slew Rate
10
V/ms
VDDSR+
VDD Positive Slew Rate, minimum
0.05
V/ms
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 8)
MAX
(Note 7)
UNITS
NOTES
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x VDD
V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
VOL
SDA Output Buffer LOW Voltage,
Sinking 3mA
VDD = 5V, IOL = 3mA
0
0.02
0.4
V
CPIN
SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz,
VDD = 5V, VIN =0V, VOUT = 0V
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing
30% of VDD, until SDA exits
the 30% to 70% of VDD
window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD
during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
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