24 FN6668.9 June 20, 2012 User Registers (Accessed by Using Slave Address 1010111x) Addresses [00h to 7Fh] These registers are 128 by" />
參數(shù)資料
型號: ISL12022MIBZ-T7A
廠商: Intersil
文件頁數(shù): 17/31頁
文件大小: 0K
描述: IC RTC/CALENDAR TEMP SNSR 20SOIC
應(yīng)用說明: Addressing Power Issues in Real Time Clock Appls
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 250
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,夏令時(shí),閏年,SRAM
存儲容量: 128B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 帶卷 (TR)
ISL12022M
24
FN6668.9
June 20, 2012
User Registers (Accessed by
Using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM. The
separate I2C slave address must be used to read and write to
these registers.
I2C Serial Interface
The ISL12022M supports a bi-directional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL12022M operates as a slave device in all
applications.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 17). On power-
up of the ISL12022M, the SDA pin is in the input mode.
All I2C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
ISL12022M continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 17). A START condition is ignored
during the power-up sequence.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 17). A STOP condition at the end of a read
operation or at the end of a write operation to memory only
places the device in its standby mode.
FIGURE 17. VALID DATA CHANGES, START AND STOP CONDITIONS
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 19. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM THE
MASTER
SIGNALS FROM
THE ISL12022M
A
C
K
10
0
11
A
C
K
WRITE
SIGNAL AT SDA
00 00
11 1
ADDRESS
BYTE
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