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| 型號： | ISL12022IBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 18/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 8-SOIC |
| 應用說明： | Addressing Power Issues in Real Time Clock Appls |
| 產(chǎn)品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 98 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，夏令時，閏年，SRAM |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1245 (CN2011-ZH PDF) |
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ISL12022
25
FN6659.3
November 22, 2011
The ISL12022 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again,
after successful receipt of an Address Byte. The ISL12022 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
Device Addressing
Following a start condition, the master must output a Slave Address
Byte. The 7 MSBs are the device identifiers. These bits are
“1101111” for the RTC registers and “1010111” for the User SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 18).
After loading the entire Slave Address Byte from the SDA bus, the
ISL12022 compares the device identifier and device select bits with
“1101111” or “1010111”. Upon a correct compare, the device
outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained from an
internal counter. On power-up, the internal address counter is set to
address 00h, so a current address read starts at address 00h. When
required, as part of a random read, the master must supply the 1
Word Address Bytes, as shown in Figure 19.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte must be
“1101111x” in both places.
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL12022 responds
with an ACK. At this time, the I2C interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction, followed by
one or more Data Bytes (see Figure 19). The master initiates the
operation issuing the following sequence: a START, the Identification
byte with the R/W bit set to “0”, an Address Byte, a second START,
and a second Identification byte with the R/W bit set to “1”. After
each of the three bytes, the ISL12022 responds with an ACK. Then
the ISL12022 transmits Data Bytes as long as the master responds
with an ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a STOP
condition) following the last bit of the last Data Byte (see Figure 19).
The Data Bytes are from the memory location indicated by an
internal pointer. This pointer’s initial value is determined by the
Address Byte in the Read operation instruction, and increments
by one during transmission of each Data Byte. After reaching the
memory location 2Fh, the pointer “rolls over” to 00h, and the
device continues to output data for each ACK received.
Application Section
Power Supply Considerations
The ISL12022M contains programmed EEPROM registers which
are recalled to volatile RAM registers during initial power-up.
These registers contain DC voltage, frequency and temperature
calibration settings. Initial power-up can be either application of
VBAT or VDD power, whichever is first. It is important that the
initial power-up meet the power supply slew rate specification to
avoid faulty EEPROM power-up recall. Also, any glitches or low
voltage DC pauses should be avoided, as these may activate
recall at a low voltage and load erroneous data into the
calibration registers. Note that a very slow VDD ramp rate
(outside data sheet limits) will almost always trigger erroneous
recall and should be avoided entirely.
Battery-Backup Details
The ISL12022 has automatic switchover to battery-backup when
the VDD drops below the VBAT mode threshold. A wide variety of
backup sources can be used, including standard and
rechargeable lithium, super capacitors, or regulated secondary
sources. The serial interface is disabled in battery-backup, while
the oscillator and RTC registers are operational. The SRAM
register contents are powered to preserve their contents as well.
The input voltage range for VBAT is 1.8V to 5.5V, but keep in mind
the temperature compensation only operates for VBAT > 2.7V.
Note that the device is not guaranteed to operate with a
VBAT < 1.8V, so the battery should be changed before
FIGURE 18. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES
SLAVE
ADDRESS BYTE
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
DATA BYTE
A6
A5
1
10
1
R/W
1
WORD ADDRESS
FIGURE 19. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
A
C
K
A
C
K
0
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
10
1
1111
10
1
11 11
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL12022IBZ-T | 功能描述:實時時鐘 REAL TIME CLK/CLNDR W/TEMP COMP 8 L RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12022IBZ-T7A | 功能描述:實時時鐘 REAL TIME CLK/CLNDR W/TEMP COMP 8 L RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12022M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_09 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_10 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving |
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