- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄9379 > ISL12022IBZ-T (Intersil)IC RTC/CALENDAR TEMP SNSR 8-SOIC PDF資料下載
參數(shù)資料
| 型號(hào)： | ISL12022IBZ-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 8/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 8-SOIC |
| 應(yīng)用說(shuō)明： | Addressing Power Issues in Real Time Clock Appls |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類(lèi)型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，夏令時(shí)，閏年，SRAM |
| 存儲(chǔ)容量： | 128B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)
ISL12022
16
FN6659.3
November 22, 2011
POWER SUPPLY CONTROL REGISTER (PWR_VDD)
Clear Time Stamp Bit (CLRTS)
This bit clears Time Stamp VDD to Battery (TSV2B) and Time
Stamp Battery to VDD Registers (TSB2V). The default setting is 0
(CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1).
VDD Brownout Trip Voltage BITS (VDDTrip<2:0)
These bits set the 6 trip levels for the VDD alarm, indicating that
VDD has dropped below a preset level. In this event, the LVDD bit
in the Status Register is set to “1”. See Table 6.
Battery Voltage Trip Voltage Register
(PWR_VBAT)
This register controls the trip points for the two VBAT alarms, with
levels set to approximately 85% and 75% of the nominal battery
level.
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting VBAT pin from the
internal circuitry. Setting this bit allows the device to disconnect the
battery and eliminate standby current drain while the device is
unused. Once VDD is powered up, this bit is reset and the VBAT pin is
then connected to the internal circuitry.
The application for this bit involves placing the chip on a board
with a battery and testing the board. Once the board is tested
and ready to ship, it is desirable to disconnect the battery to keep
it fresh until the board or unit is placed into final use. Setting
RESEALB = “1” initiates the battery disconnect, and after VDD
power is cycled down and up again, the RESEAL bit is cleared
to “0”.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>)
Three bits select the first alarm (85% of Nominal VBAT) level for the
battery voltage monitor. There are total of 7 levels that could be
selected for the first alarm. Any of the of levels could be selected as
the first alarm with no reference as to nominal Battery voltage level.
See Table 8.
BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
Three bits select the second alarm (75% of Nominal VBAT) level for
the battery voltage monitor. There are total of 7 levels that could be
selected for the second alarm. Any of the of levels could be selected
as the second alarm with no reference as to nominal Battery voltage
level. See Table 9.
Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room temperature)
of the crystal. Both Digital Trimming (DT) and Analog Trimming
(AT) methods are available. The digital trimming uses clock pulse
skipping and insertion for frequency adjustment. Analog
4
Hz
1
000
2
Hz
1
001
1
Hz
1
010
1/2
Hz
1
011
1/4
Hz
1
100
1/8
Hz
1
101
1/16
Hz
1
110
1/32
Hz
1
ADDR
7
6
5
4
3
2
1
0
09h
CLRTS
0
VDDTrip2 VDDTrip1 VDDTrip0
TABLE 6. VDD TRIP LEVELS
VDDTrip2
VDDTrip1
VDDTrip0
TRIP VOLTAGE
(V)
0
2.295
0
1
2.550
0
1
0
2.805
0
1
3.060
1
0
4.250
1
0
1
4.675
TABLE 7.
ADDR 7
6
5
4321
0
0Ah
D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0
TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN (Continued)
FREQUENCY,
FOUT
UNITS
FO3
FO2
FO1
FO0
TABLE 8. VB85T ALARM LEVEL
VB85Tp2
VB85Tp1
VB85Tp0
BATTERY ALARM
TRIP LEVEL
(V)
00
0
2.125
0
1
2.295
0
1
0
2.550
0
1
2.805
1
0
3.060
1
0
1
4.250
1
0
4.675
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
VB75Tp2
VB75Tp1
VB75Tp0
BATTERY ALARM
TRIP LEVEL
(V)
00
0
1.875
0
1
2.025
0
1
0
2.250
01
1
2.475
1
0
2.700
1
0
1
3.750
11
0
4.125
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL12024IVZ-T | IC RTC/CALENDAR EEPROM 8-TSSOP |
| AD5112BCPZ10-500R7 | IC DGTL POT 64POS 10K 8LFCSP |
| AD5112BCPZ80-500R7 | IC DGTL POT 64POS 80K 8LFCSP |
| ISL12026AIVZ | IC RTC/CALENDAR EEPROM 8-TSSOP |
| VI-2NM-MW | CONVERTER MOD DC/DC 10V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL12022IBZ-T7A | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/TEMP COMP 8 L RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12022M | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_09 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_10 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving |
| ISL12022MA | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。