- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗9379 > ISL12022IBZ-T (Intersil)IC RTC/CALENDAR TEMP SNSR 8-SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ISL12022IBZ-T |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 25/29闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC RTC/CALENDAR TEMP SNSR 8-SOIC |
| 鎳夌敤瑾槑锛� | Addressing Power Issues in Real Time Clock Appls |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Solutions for Industrial Control Applications |
| 妯欐簴鍖呰锛� | 2,500 |
| 椤炲瀷锛� | 鏅傞悩/鏃ユ |
| 鐗归粸锛� | 璀﹀牨鍣紝澶忎护鏅�锛岄枏骞达紝SRAM |
| 瀛樺劜瀹归噺锛� | 128B |
| 鏅傞枔鏍煎紡锛� | HH:MM:SS锛�12/24 灏忔檪锛� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | YY-MM-DD-dd |
| 鎺ュ彛锛� | I²C锛�2 绶氫覆鍙� |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V |
| 闆诲 - 闆绘簮锛岄浕姹狅細 | 1.8 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�鐣跺墠绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�
ISL12022
5
FN6659.3
November 22, 2011
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, TA = -40掳C to +85掳C, unless otherwise stated. Boldface limits apply over the
operating temperature range, -40掳C to +85掳C
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 13)
TYP
(Note 9)
MAX
(Note 13)
UNITS
NOTES
VDD SR-
VDD Negative Slew Rate
10
V/ms
VDDSR+
VDD Positive Slew Rate, Minimum
0.05
V/ms
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40掳C to +85掳C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40掳C to +85掳C
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 9)
MAX
(Note 13)
UNITS
NOTES
VIL
SDA and SCL Input Buffer LOW Voltage
-0.3
0.3 x VDD
V
VIH
SDA and SCL Input Buffer HIGH Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis SDA and SCL Input Buffer Hysteresis
0.05 x VDD
V
VOL
SDA Output Buffer LOW Voltage,
Sinking 3mA
VDD = 5V, IOL = 3mA
0
0.02
0.4
V
CPIN
SDA and SCL Pin Capacitance
TA = +25掳C, f = 1MHz, VDD = 5V,
VIN =0V, VOUT = 0V
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max
spec is suppressed.
50
ns
tAA
SCL Falling Edge To SDA Output Data
Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window.
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VDD during
a STOP condition, to SDA
crossing 70% of VDD during the
following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
70% of VDD window, to SCL rising
edge crossing 30% of VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
30% of VDD to SDA entering the
30% to 70% of VDD window.
0900
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL
falling edge. Both crossing 70%
of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
0
ns
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ISL12024IVZ-T | IC RTC/CALENDAR EEPROM 8-TSSOP |
| AD5112BCPZ10-500R7 | IC DGTL POT 64POS 10K 8LFCSP |
| AD5112BCPZ80-500R7 | IC DGTL POT 64POS 80K 8LFCSP |
| ISL12026AIVZ | IC RTC/CALENDAR EEPROM 8-TSSOP |
| VI-2NM-MW | CONVERTER MOD DC/DC 10V 100W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ISL12022IBZ-T7A | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 REAL TIME CLK/CLNDR W/TEMP COMP 8 L RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰ㄦ牸:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| ISL12022M | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Low Power RTC with Battery Backed SRAM, Integrated 卤5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_09 | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Low Power RTC with Battery Backed SRAM, Integrated 卤5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_10 | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Low Power RTC with Battery Backed SRAM,Integrated 卤5ppm Temperature Compensation and Auto Daylight Saving |
| ISL12022MA | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Low Power RTC with Battery Backed SRAM, Integrated 卤5ppm Temperature Compensation and Auto Daylight Saving |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京銆�
