9 FN6667.5 December 13, 2011 SDA vs SCL Timing Symbol Table tSU:STO t" />
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鐢�(ch菐n)鍝佺洰閷勯爜闈細 1245 (CN2011-ZH PDF)
ISL12020M
9
FN6667.5
December 13, 2011
SDA vs SCL Timing
Symbol Table
tSU:STO
tDH
tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tF
tLOW
tBUF
tAA
tR
FIGURE 2. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE
WITH VDD = 5.0V
SDA
AND
IRQ/FOUT
1533
100pF
5.0V
FOR VOL= 0.4V
AND IOL = 3mA
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LO W
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LO W
Will change
from HIGH
to LOW
Don鈥檛 Care:
Changes Allowed
Changing:
State Not Known
N/A
Center Line is
High Impedance
Typical Performance Curves Temperature is +25掳C unless otherwise specified.
FIGURE 3. IBAT vs VBAT
FIGURE 4. IBAT vs TEMPERATURE
800
850
900
950
1000
1050
1.82.3
2.83.3
3.84.3
4.85.3
VBAT VOLTAGE (V)
V
BA
T
CURR
E
N
T
(n
A)
600
800
1000
1200
1400
1600
-40
-20
0
2040
6080
TEMPERATURE (掳C)
I BA
T
(n
A
)
VBAT = 1.8V
VBAT = 3.0V
VBAT = 5.5V
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