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| 型號： | ISL12020MIRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 19/34頁 |
| 文件大小： | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 20-DFN |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 53 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，夏令時(shí)，閏年，SRAM |
| 存儲(chǔ)容量： | 128B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-DFN（5.5x4.0） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1245 (CN2011-ZH PDF) |
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ISL12020M
26
FN6667.5
December 13, 2011
ALPHA Hot Register (ALPHAH)
The ALPHA Hot variable is 7 bits and is defined as the temperature
coefficient of Crystal from the XT0 value to +85°C (both Alpha Hot
and Alpha Cold must be programmed to provide full temperature
compensation). It is normally given in units of ppm/°C2, with a
typical value of -0.034. Like the ALPHA Cold version, a scaled
version of the absolute value of this coefficient is used in order to
get an integer value. Therefore, ALP_H<7:0> is defined as the
(|Actual Alpha Hot Value| x 2048) and converted to binary. For
example, a crystal with Alpha Hot of -0.034ppm/°C2 is first scaled
(|2048*(-0.034)| = 70d) and then converted to a binary number
of 01000110b.
The practical range of Actual ALPHAH values is from -0.020 to -
0.060.
The ISL12020M has a preset ALPHAH value corresponding to the
crystal in the module. This value is recalled on initial power-up
and should never be changed for best temperature
compensation performance, although the user may override this
preset value if so desired.
The ALPHAH register should only be changed while the TSE
(Temp Sense Enable) bit is “0”.
User Registers (Accessed by
Using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM. The
separate I2C slave address must be used to read and write to
these registers.
I2C Serial Interface
The ISL12020M supports a bi-directional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL12020M operates as a slave device in all
applications.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 16). On power-
up of the ISL12020M, the SDA pin is in the input mode.
.
TABLE 27. ALPHA HOT REGISTER
ADDR 7
6
5
4
3210
2Dh
D ALP_H
6
ALP_H
5
ALP_H
4
ALP_H
3
ALP_H
2
ALP_H
1
ALP_H
0
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT
FROM RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
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