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參數(shù)資料
| 型號： | IR5001 |
| 廠商： | International Rectifier |
| 英文描述： | UNIVERSAL ACTIVE ORING CONTROLLER |
| 中文描述： | 通用有源ORing控制器 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 226K |
| 代理商： | IR5001 |
IR5001
3
www.irf.com
PIN DESCRIPTIONS
Note 1:
Guaranteed by design but not tested in production.
Note 2:
Low Vcc output voltage corresponds to low UVLO voltage
PIN#
PIN SYMBOL
PIN DESCRIPTION
1
Vline
IC power supply pin for 36V to 75V input communications systems.
Minimum 25V has to be applied at this pin to bias the IC.
2
Vcc
Output pin of the internal shunt regulator, or input pin for biasing the IC via
external resistor. This pin is internally regulated at 12.5V typical. A
minimum 0.1uF capacitor must be connected from this pin to Gnd of IR5001.
3
FETch
FET check input pin. Together with FET status output pin, the FETch pin
can be used to determine the state of the Active ORing circuit and power
system redundancy.
4
FETst
FET status output pin. Together with FETch input pin, the FETst pin can be
used to determine the state of the Active ORing circuit and power system
redundancy.
5
INP
Positive input of internal comparator. This pin should connect to the source
of N-channel Active ORing MOSFET.
6
INN
Negative input pin of internal comparator. This pin should connect to the
drain of N-channel Active ORing MOSFET.
7
Gnd
Ground pin of the IR5001.
8
Vout
Output pin for the IR5001. This pin is used to directly drive the gate of the
Active Oring N-Channel MOSFET.
PARAMETERS
Output Section
High Level Output Voltage
SYMBOL
TEST CONDITION
Vline=25V, IOH=50uA,
V(INN)=-0.3V
MIN TYP MAX UNITS
Vout HI
9.5
12
14
V
Low Level Output Voltage
Turn-On DelayTime
Rise Time
Turn-Off Delay Time
Fall Time
FETch and FETst
FETch Sink Current
FETch Output Delay Time
FETch Threshold
Vout LO
td(on)
tr
td(off)
tf
IOL=100mA, V(INN)=+0.3V
0.1
27
0.7
0.1
45
5
V
us
ms
5
0.1
110 130 170
10
26
39
I(FETch)
FETch=5V
-0.5 -1.1
-2
uA
FETch_pd
Vth(FETch)
Note 1
0.8
1.2
1.8
1.5
us
V
0.9
FETst Threshold Voltage
Vth(FETst)
5k resistor from FETst to 5V logic
bias.
V(INP) = Gnd, V(INN) ramping down
from 0 until FETst switches to Low.
-525 -300 -200
mV
FETst Low Level Output
Voltage
VOL
Isink=1mA, V(INN)=-0.5V
0
50
100
mV
Vout switching from LO to HI, Fig.5
Vout switching from HI to LO, Fig.5
ns
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