參數(shù)資料
型號(hào)： IR1110
廠商： International Rectifier
英文描述： SOFT START CONTROLLER IC
中文描述： 軟起動(dòng)控制器芯片
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 227K
代理商： IR1110
15
IR1110
ADVANCE INFORMATION
www.irf.com
V
PK
Store
C
PK
stores a voltage, V
PK
, that is essentially equal to the peak of the timing waves. R
PKD
is
normally connected to ground via Q1. The time constant of R
PKD
with C
PK
allows V
PK
to track
changes of amplitude of the timing waves that take place over a number of cycles, while maintain-
ing an essentially smooth waveform.
Ramp Circuit
The current source, IRAMP, creates an increasing voltage, VRAMP, across CRAMP,
whenever Q3 has been conducting, then switches OFF. The maximum value of VRAMP is
clamped at VPK.
VRAMP controls the ramp-up rate of the bus voltage. RRAMP shapes VRAMP to a
parabolic form, which gives an approximately linear rise of DC bus voltage with a capacitive load.
The rate of change of VRAMP at the start of the ramp is set by CRAMP. RRAMP also has
some influence on the initial rate of change, but more influence later during the ramp-up period.
The greater the initial rate of rise of VRAMP, the greater the maximum first firing angle.
Typical relationships between C
RAMP
,R
RAMP
,t
DPWR
, t
RAMP1
, and t
D1FIRE
are as follows:
C
RAMP
uF
R
RAMP
t
DPWR
k
(typical)
msec
130 165
82 190
47 230
30 270
t
RAMP
(typical)
msec
100
150
220
330
t
D1FIRE
(max)
degrees
35
32
25
22
0.68
1
2.2
3.3
The minimum and maximum permissible values of C
RAMP
are 0.68uF and 3.3uF respectively. Total
ramp-up time can be increased above the values shown by increasing R
RAMP
. For example, with
C
RAMP
=3.3uF and R
RAMP
open, ramp-up time increases to about 1.2 seconds.
The maximum first firing angle is specified at maximum AC input voltage, and assumes
that worst case cumulative tolerances of the governing external components cause sufficient
phase-to-phase unbalance that firing on one phase only occurs during the early part of ramp-up.
The circuit in Figure 15(a) will reduce the maximum first firing angle to 17
°
, if desired. If
the voltage regulation function is not used, and the circuit of Figure 13 is not used, the Figure
15(b) circuit can be used in place of the Figure 15(a) circuit for the same purpose. With either
circuit, both t
DPWR
and t
RAMP
will increase to about 400msec.
Ramp Clamp Circuit
When Q4 is OFF, the ramp clamp is enabled, and Q3 is controlled by the output of the Ramp
Error Amplifier. This amplifier compares |V
BUSO
|, via R
CLAMP1
, with V
RAMP
, via R
CLAMP2
. The amplified
output drives Q3 in a linear mode, diverting I
RAMP
from C
RAMP
and forcing V
RAMP
to be essentially
equal to V
BUSO
x R
CLAMP2
/R
CLAMP1
.
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