參數(shù)資料
型號: IR1110
廠商: International Rectifier
英文描述: SOFT START CONTROLLER IC
中文描述: 軟起動(dòng)控制器芯片
文件頁數(shù): 12/32頁
文件大?。?/td> 227K
代理商: IR1110
12
IR1110
ADVANCE INFORMATION
www.irf.com
Lead Definitions
Symbol
DVDD
DGND
DVSS
AVDD
AGND
AVSS
UIN/VIN/WIN
VBAMPP
VBAMPN
VBUSO
VBREF
DCREG2
DCREG1
DCREGC
1PHSEL
1PHEN
LNLSSL
1PHCAP
3PHCAP
VRAMP
RAMPERR
CRAMP
RRAMP
RBIAS
VPKLL
UVLOCAP
BDIP1
BDIP2
BDIPHLD
BDIPCAP
VPKDISC1
VPKDISC2
VPK
VPKREC
WDCAPU/V/W
LNSET
LNLSLED
1PHLED
LNLED
CINTU/V/W
INTNU/V/W
RINTU/V/W
RSTRU/V/W
SCRU/V/W
TEST1
TEST2
SCRREF
Pin #
44
43
31
17
25,26,43
4,31,51
1,2,3
5
6
7
8
9
11
10
12
13
14
15
16
18
19
20
21
22
23
24
29
27
30
28
33
32
34
35
38,37,36
39
40
41
42
61,57,53
62,58,54
63,59,55
64,60,56
47,46,45
48
49
50
Description
Logic positive supply voltage.
Logic ground
Logic negative supply voltage
Analog positive supply voltage
Analog ground
Analog negative supply voltage
Phase U/V/W voltage inputs
DC bus OP Amp. positive input, connect to DC bus(-) via resistor
DC bus OP Amp. negative input, connect to DC bus (+) via resistor
DC bus OP Amp. output
DC bus regulation voltage reference input
DC bus error amplifier output via series diode
DC bus error amplifier output
DC bus error compensation (External capacitor connection pin)
Single phase input mode select.
Single phase shutdown mode enable.
Phase loss Fault Output Select.
Single phase loss detect timing capacitor
Three phase loss detect timing capacitor
Buffered voltage ramp circuit output
Ramp error amplifier input
Ramp timing capacitor
Ramp timing resistor
Bias current resistor
Line-to-line peak voltage holding capacitor
Under voltage lockout delay capacitor
DC bus voltage dip detection 1
DC bus voltage dip detection 2
DC bus voltage dip hold capacitor
DC bus voltage dip timing capacitor
Line synchronization timing wave peak voltage discharging resistor
No connection
Line synchronization timing wave peak voltage
Line synchronization timing waveform
Watchdog timing capacitor for phase U, V, and W
Line voltage comparator reference input
Line Loss Fault Output
Single Phase Loss Fault Output
High/Low line status Output
Phase U/V/W integral amplifier output
Phase U/V/W integral amplifier negative input
Phase U/V/W integral amplifier resistor connection
Phase U/V/W integral discharge resistor
Phase U/V/W SCR gate signal
Test purpose pin (Should be tied to VDD)
Test purpose pin (No connection should be made)
SCR gate signal reference
Note 1)
Note 2)
Note 3)
on page 12
on page 12
on page 12
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