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參數(shù)資料
| 型號(hào)： | IQ80C52TXXX-L16SHXXX |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 182/204頁(yè) |
| 文件大?。?/td> | 5687K |
| 代理商： | IQ80C52TXXX-L16SHXXX |
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79
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
The counter is incremented at each timer clock (clk
T1) until it passes its TOP value and then restarts from BOT-
TOM. The counting sequence is determined by the setting of the CTC1 bit located in the Timer/Counter Control
Register (TCCR1A). For more details about counting sequences, see “Modes of Operation” on page 81. clk
T1 can
be generated from an external or internal clock source, selected by the Clock Select bits (CS1[2:0]). When no clock
source is selected (CS1[2:0] = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU,
regardless of whether clk
T1 is present or not. A CPU write overrides (has priority over) all counter clear or count
operations. The Timer/Counter Overflow Flag (TOV1) is set when the counter reaches the maximum value and it
can be used for generating a CPU interrupt.
12.5
Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-
stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via
the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate fre-
quency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating
a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 12-2. The elements of the block diagram
that are not directly a part of the Input Capture unit are gray shaded.
Figure 12-2. Input Capture Unit Block Diagram
The Output Compare Register OCR1A is a dual-purpose register that is also used as an 8-bit Input Capture Regis-
ter ICR1. In 16-bit Input Capture mode the Output Compare Register OCR1B serves as the high byte of the Input
Capture Register ICR1. In 8-bit Input Capture mode the Output Compare Register OCR1B is free to be used as a
normal Output Compare Register, but in 16-bit Input Capture mode the Output Compare Unit cannot be used as
there are no free Output Compare Register(s). Even though the Input Capture register is called ICR1 in this sec-
tion, it is refering to the Output Compare Register(s).
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), and this change confirms to
the setting of the edge detector, a capture will be triggered. When a capture is triggered, the value of the counter
(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system
ICF0 (Int.Req.)
WRITE
ICR0 (16-bit Register)
OCR0B (8-bit)
Noise
Canceler
ICP0
Edge
Detector
TEMP (8-bit)
DATA BUS
(8-bit)
OCR0A (8-bit)
TCNT0 (16-bit Counter)
TCNT0H (8-bit)
TCNT0L (8-bit)
ICNC0
ICES0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC80C52XXX-16/883 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MQ83C154XXX-16/883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| MR87C251SB16 | 8-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| MC87C251SB16 | 8-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR87C51FC | 8-BIT, UVPROM, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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