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參數(shù)資料
| 型號(hào)： | IQ80C52TXXX-L16SHXXX |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 113/204頁(yè) |
| 文件大?。?/td> | 5687K |
| 代理商： | IQ80C52TXXX-L16SHXXX |
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20
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
6.3
System Clock Prescaler
The system clock is derived from the main clock via the System Clock Prescaler. The system clock can be divided
by setting the “CLKPSR – Clock Prescale Register” on page 22. The system clock prescaler can be used to
decrease power consumption at times when requirements for processing power is low or to bring the system clock
within limits of maximum frequency. The prescaler can be used with all main clock source options, and it will affect
the clock frequency of the CPU and all synchronous peripherals.
The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still
ensuring stable operation.
6.3.1
Switching Prescaler Setting
When switching between prescaler settings, the system clock prescaler ensures that no glitch occurs in the system
clock and that no intermediate frequency is higher than neither the clock frequency corresponding the previous set-
ting, nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the main clock, which may be faster than
the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were read-
able, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock fre-
quency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and
T2 is the period corresponding to the new prescaler setting.
6.4
Starting
6.4.1
Starting from Reset
The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until
the reset source is released and the start-up sequence is completed. The start-up sequence includes three steps,
as follows.
1.
The first step after the reset source has been released consists of the device counting the reset start-up
time. The purpose of this reset start-up time is to ensure that supply voltage has reached sufficient levels.
The reset start-up time is counted using the internal 128 kHz oscillator. See Table 6-1 for details of reset
start-up time.
Note that the actual supply voltage is not monitored by the start-up logic. The device will count until the
reset start-up time has elapsed even if the device has reached sufficient supply voltage levels earlier.
2.
The second step is to count the oscillator start-up time, which ensures that the calibrated internal oscilla-
tor has reached a stable state before it is used by the other parts of the system. The calibrated internal
oscillator needs to oscillate for a minimum number of cycles before it can be considered stable. See Table
6-1 for details of the oscillator start-up time.
3.
The last step before releasing the internal reset is to load the calibration and the configuration values from
the Non-Volatile Memory to configure the device properly. The configuration time is listed in Table 6-1.
Notes:
1. After powering up the device or after a reset the system clock is automatically set to calibrated internal 8 MHz oscil-
lator, divided by 8
2. When the Brown-out Detection is enabled, the reset start-up time is 128 ms after powering up the device.
Table 6-1.
Start-up Times when Using the Internal Calibrated Oscillator
Reset
Oscillator
Configuration
Total start-up time
64 ms
6 cycles
21 cycles
64 ms + 6 oscillator cycles + 21 system clock cycles (1)(2)
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