參數(shù)資料
型號： IQ80C52EXXX-12D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44
封裝： CERAMIC, QFP-44
文件頁數(shù)： 17/108頁
文件大?。?/td> 3682K
代理商： IQ80C52EXXX-12D
16
8069R–AVR–06/2013
XMEGA A4
Not recommended for new designs -
Use XMEGA A4U series
9.
Event System
9.1
Features
Inter-peripheral communication and signalling with minimum latency
CPU and DMA independent operation
8 Event Channels allow for up to 8 signals to be routed at the same time
Events can be generated by
– TImer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converters (ADCx)
– Analog Comparators (ACx)
– Ports (PORTx)
– System Clock (ClkSYS)
– Software (CPU)
Events can be used by
– TImer/Counters (TCxn)
– Analog to Digital Converters (ADCx)
– Digital to Analog Converters (DACx)
– Ports (PORTx)
– DMA Controller (DMAC)
– IR Communication Module (IRCOM)
The same event can be used by multiple peripherals for synchronized timing
Advanced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
Functions in Active and Idle mode
9.2
Overview
The Event System is a set of features for inter-peripheral communication. It enables the possibil-
ity for a change of state in one peripheral to automatically trigger actions in one or more
peripherals. Whose changes in a peripheral that will trigger actions in other peripherals are con-
figurable by software. It is a simple, but powerful system as it allows for autonomous control of
peripherals without any use of interrupts, CPU or DMA resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that peripheral. Events are passed between peripherals using a dedi-
cated routing network called the Event Routing Network. Figure 9-1 on page 17 shows a basic
block diagram of the Event System with the Event Routing Network and the peripherals to which
it is connected. This highly flexible system can be used for simple routing of signals, pin func-
tions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one periph-
eral, until the actions are triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.
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