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參數(shù)資料
| 型號： | IP101 |
| 英文描述： | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| 中文描述： | 單芯片物理層10/100M自適應快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 19/33頁 |
| 文件大?。?/td> | 821K |
| 代理商： | IP101 |
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IP101
IP101-DS-R0.02
Feb. 24, 2003
19 / 33
Copyright
2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
RMII Interface
Reduced Media Independent Interface (RMII) is
defined to provide a fewer pins data transmission
condition. The management interface, MDC and MDIO,
are identical to the MII defined in IEEE 802.3. RMII
supports 10/100Mb data rates and the clock source is
provided by a single 50MHz clock from either external
or within IP101. This clock is used as reference for
transmit,
receive
and
independent 2 bit wide transmit and receive data path,
i.e., TXD[1:0] and RXD[1:0]. CRS_DV is asserted when
the receive medium is not idle and de-asserted when
the medium is idle.
Before any transmission occurs, CRS_DV should be
de-asserted and value “00” should be present in both
TXD[1:0] and RXD[1:0]. When transmission begins,
IP101 will send “01” (TXD[1:0] = 01) for preamble to
indicate SFD, and also assert TX_EN synchronous with
first nibble of the preamble. TX_EN should be
de-asserted until the end of the data transmission. At
receiving mechanism, by receiving “01” means a valid
data is available. If False carrier is detected, RXD[1:0]
shall be “10” until the end of the transmission.
At 10Mbps mode, every 10
th
cycle of REF_CLK will be
sampled in RXD[1:0] and TXD[1:], because the
REF_CLK frequency is 10 times faster than the data
rate of the 10Mbps.
SNI Interface
The IP101 also provides serial-network interface for
legacy MACs, when the chip operates at 10BASE-T
either by NWAY resolved result or by forced mode. To
setup for this mode of operation, pull both the MII/SNIB
and the COL/RMII pins to low.
The transaction protocol of SNI interface is almost
identical to that of MII interface, except of data bit width
and clock rate. This interface consists of 10Mbps
transmit and receive clock generated by PHY’s digital
phase-locked loop (DPLL), 10Mbps transmit and
receive serial data, transmit enable, collision detect,
and carry sense signals.
control.
RMII
provides
Auto-Negotiation and Related Information
IP101 supports clause 28 in the IEEE 802.3u standard.
IP101 can be operated either in 10Mbps/100Mbps or
half/full duplex transmission mode. IP101 also supports
flow control mechanism to prevent any collision in the
network. If the other end does not support N-Way
function, IP101 will link at half duplex mode and enter
parallel detection.
At beginning of auto-negotiation, IP101 will advertise its
own ability by sending FLP waveform out to the other
end and also listening signals from the other end. IP101
will place itself into correct connection speed depends
on the received signals. If NLP signal is replied from the
other end, IP101 will enter 10Mbps, while active idle
pulses (unique 100Mbps pattern) IP101 will go to
100Mbps mode instead.
Once the negotiation has completed with the other
party, IP101 will configure itself to the desired
connection mode, i.e., 10/100Mbps or Half/Full duplex
modes. If there is no detection of link pulses within
1200ms~1500mS, IP101 will enter Link Fail State and
restart auto-negotiation procedure.
The auto-negotiation information is stored in the
IP101’s MII registers. These registers can be modified
and monitor the IP101’s N-Way status. The reset
auto-negotiation in register 0 of MII registers can be set
at any time to restart auto-negotiation.
The flow control ability is also included in the IP101
chip. If MAC supports flow control condition, then flow
control will be enabled by setting bit 10 (Pause) of the
Register 4.
Pin 37 (AN_ENA), 38 (DLPX), 39 (SPD) can be
configured manually to set IP101’s transmission ability.
1. Enabling Pin 37 (set high) will put IP101 to N-Way
mode, if set low to pin 37, it will put IP101 into
forced mode.
2. Pin 38 will configure Duplex ability of IP101, at high,
IP101 is set to Full-Duplex and low will let IP101
enter half duplex mode.
3. Pin 39 determines the speed of connection. If the
pin is pulled high, IP101 is set at 100Mbps, while at
low will make IP101 to connect at 10Mbps speed.
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相關代理商/技術參數(shù) |
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| IP101ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R04 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
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