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參數(shù)資料
| 型號： | IOS62C256-70U |
| 英文描述： | IC-SM-256K CMOS SRAM |
| 中文描述： | 集成電路的Sm - 256K CMOS SRAM的 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 65K |
| 代理商： | IOS62C256-70U |
ISSI
IS62C256
2-6
Integrated Silicon Solution, Inc.
Rev. D 0895
SR81995C256
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-45 ns
Min.
-70ns
-100 ns
Min.
Symbol
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
Parameter
Max.
Min.
Max.
Max.
Unit
Write Cycle Time
45
—
70
—
100
—
ns
CE
to Write End
35
—
60
—
80
—
ns
Address Setup Time to Write End
25
—
60
—
80
—
ns
Address Hold from Write End
0
—
0
—
0
—
ns
Address Setup Time
0
—
0
—
0
—
ns
WE
Pulse Width
25
—
55
—
60
—
ns
Data Setup to Write End
20
—
30
—
35
—
ns
Data Hold from Write End
0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured
±
500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with
OE
HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
Controlled)
(1,2)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE
WE
D
OUT
D
IN
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