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參數(shù)資料
| 型號(hào)： | IOS62C256-70U |
| 英文描述： | IC-SM-256K CMOS SRAM |
| 中文描述： | 集成電路的Sm - 256K CMOS SRAM的 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 65K |
| 代理商： | IOS62C256-70U |
ISSI
IS62C256
2-4
Integrated Silicon Solution, Inc.
Rev. D 0895
SR81995C256
DATA RETENTION CHARACTERISTICS
Symbol
V
DR
I
DR
1
I
DR
2
Parameter
V
CC
for retention of data
Data retention current
Data retention current
Test Conditions
Min.
2.0
—
—
Max.
—
200
200
Units
V
μ
A
μ
A
V
DR
= 3.0V, T
A
= 0
°
C to +25
°
C
V
DR
= 3.0V, T
A
= 0
°
C to +70
°
C
Figure 1a.
Figure 1b.
480
100 pF
Including
jig and
scope
255
OUTPUT
5V
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-45 ns
-70 ns
-100 ns
Min.
Symbol
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
(3)
t
PD
(3)
Parameter
Min.
Max.
Min.
Max.
Max.
Unit
Read Cycle Time
45
—
70
—
100
—
ns
Address Access Time
—
45
—
70
—
100
ns
Output Hold Time
2
—
2
—
2
—
ns
CE
Access Time
—
45
—
70
—
100
ns
OE
Access Time
—
25
—
35
—
50
ns
OE
to Low-Z Output
0
—
0
—
0
—
ns
OE
to High-Z Output
0
20
0
25
0
25
ns
CE
to Low-Z Output
3
—
3
—
3
—
ns
CE
to High-Z Output
0
20
0
25
0
25
ns
CE
to Power-Up
0
—
0
—
0
—
ns
CE
to Power-Down
—
30
—
50
—
50
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured
±
500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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