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參數(shù)資料
| 型號(hào)： | IOS62C256-70U |
| 英文描述： | IC-SM-256K CMOS SRAM |
| 中文描述： | 集成電路的Sm - 256K CMOS SRAM的 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 65K |
| 代理商： | IOS62C256-70U |
ISSI
IS62C256
IS62C256
32K x 8 LOW POWER CMOS STATIC RAM
Integrated Silicon Solution, Inc.
Rev. D 0895
SR81995C256
2-1
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. Copyright 1995, Integrated Silicon Solution, Inc.
FEATURES
Access time: 45, 70, 100 ns
Low active power: 200 mW (typical)
Low standby power
— 250
μ
W (typical) CMOS standby
— 28 mW (typical) TTL standby
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V power supply
DESCRIPTION
The
ISSI
IS62C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using
ISSI
's high-
performance, low power CMOS technology.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250
μ
W (typical) at CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (
CE
) input and an active LOW Output Enable
(
OE
) input. The active LOW Write Enable (
WE
) controls both
writing and reading of the memory.
The IS62C256 is pin compatible with other 32K X 8 SRAMs
in 600-mil PDIP, 450-mil plastic SOP, or TSOP package.
ISSI
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
256 X 1024
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
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