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參數(shù)資料
| 型號(hào)： | IDT82V3202NLG8 |
| 廠(chǎng)商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 44/117頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN EBU SGL 68-VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類(lèi)型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 68-VFQFPN（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | 82V3202NLG8 |
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IDT82V3202
EBU WAN PLL
Functional Description
32
September 11, 2009
phase locked to any input clock. The frequency offset acquiring method
is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the
FAST_AVG bit, as shown in Table 17:
3.10.1.5.1 Automatic Instantaneous
By this method, the T0 DPLL freezes at the operating frequency
when it enters Holdover mode. The accuracy is 4.4X10-8 ppm.
3.10.1.5.2 Automatic Slow Averaged
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 110 minutes. The accuracy is
1.1X10-5 ppm.
3.10.1.5.3 Automatic Fast Averaged
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 8 minutes. The accuracy is
1.1X10-5 ppm.
3.10.1.5.4 Manual
By this method, the frequency offset is set by the
T0_HOLDOVER_FREQ[23:0] bits. The accuracy is 1.1X10-5 ppm.
The frequency offset of the T0 DPLL output is indicated by the
CURRENT_DPLL_FREQ[23:0] bits.
The device provides a reference for the value to be written to the
T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to
the value read from the CURRENT_DPLL_FREQ[23:0] bits or the
T0_HOLDOVER_FREQ[23:0] bits (refer to Chapter 3.10.1.5.5 Holdover
Frequency Offset Read); or then be processed by external software fil-
tering.
3.10.1.5.5 Holdover Frequency Offset Read
The offset value, which is acquired by Automatic Slow Averaged,
Automatic Fast Averaged and is set by related register bits, can be read
from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG
bit and the FAST_AVG bit, as shown in Table 18.
The frequency offset in ppm is calculated as follows:
Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X
0.000011
3.10.1.6
Pre-Locked2 Mode
In Pre-Locked2 mode, the T0 DPLL output attempts to track the
selected input clock.
The Pre-Locked2 mode is a secondary, temporary mode.
Table 17: Frequency Offset Control in Holdover Mode
MAN_HOLDOVER
AUTO_AVG
FAST_AVG
Frequency Offset Acquiring Method
0
don’t-care
Automatic Instantaneous
1
0
Automatic Slow Averaged
1
Automatic Fast Averaged
1
don’t-care
Manual
Table 18: Holdover Frequency Offset Read
READ_AVG FAST_AVG
Offset Value Read from
T0_HOLDOVER_FREQ[23:0]
0
don’t-care The value is equal to the one written to.
1
0
The value is acquired by Automatic Slow Averaged
method, not equal to the one written to.
1
The value is acquired by Automatic Fast Averaged
method, not equal to the one written to.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3202NLGBLANK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V3255 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255_08 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DKG | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT |
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