- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄9575 > IDT82V3202NLG8 (IDT, Integrated Device Technology Inc)IC PLL WAN EBU SGL 68-VFQFPN PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT82V3202NLG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 38/117頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLL WAN EBU SGL 68-VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類(lèi)型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 68-VFQFPN（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | 82V3202NLG8 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)當(dāng)前第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)
IDT82V3202
EBU WAN PLL
Functional Description
27
September 11, 2009
3.8
SELECTED INPUT CLOCK SWITCH
If the input clock is selected by External Fast selection or by Forced
selection, it can be switched by setting the related registers (refer to
any time. In this case, whether the input clock is qualified for DPLL lock-
ing does not affect the clock switch.
When the input clock is selected by Automatic selection, the input
clock switch depends on its validity and priority. If the current selected
input clock is disqualified, a new qualified input clock may be switched
to.
3.8.1
INPUT CLOCK VALIDITY
For the input clocks, the validity depends on the results of input clock
quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring).
When all of the following conditions are satisfied, the input clock is valid;
otherwise, it is invalid.
No no-activity alarm (the INn_CMOS_NO_ACTIVITY_ALARM
bit is ‘0’);
No frequency hard alarm (the INn_CMOS_FREQ_HARD_
ALARM bit is ‘0’);
If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
No phase lock alarm, i.e., the INn_CMOS_PH_LOCK_ALARM
bit is ‘0’;
If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
misses less than (<) 2 consecutive clock cycles; if the
ULTR_FAST_SW bit is ‘0’, this condition is ignored.
The validities of the input clocks are indicated by the INn_CMOS 1 bit
(n = 1 or 2). When the input clock validity changes (from ‘valid’ to ‘invalid’
or from ‘invalid’ to ‘valid’), the INn_CMOS 2 bit will be set. If the
INn_CMOS 3 bit is ‘1’, an interrupt will be generated.
When the T0 selected input clock has failed, i.e., the validity of the T0
selected input clock changes from ‘valid’ to ‘invalid’, the
T0_MAIN_REF_FAILED 1 bit will be set. If the T0_MAIN_REF_FAILED 2
bit is ‘1’, an interrupt will be generated. This interrupt can also be indi-
cated by hardware - the TDO pin, as determined by the
LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this
interrupt, it will be set high when this interrupt is generated and will
remain high until this interrupt is cleared.
3.8.2
SELECTED INPUT CLOCK SWITCH
Revertive and Non-Revertive switches are supported, as selected by
the REVERTIVE_MODE bit.
The difference between Revertive and Non-Revertive switches is
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
available for selection. In Non-Revertive switch, input clock switch is
minimized.
Conditions of the qualified input clocks available for T0 selection are
as the following:
Valid, i.e., the INn_CMOS 1 bit is ‘1’;
Priority enabled, i.e., the corresponding INn_CMOS_SEL
_PRIORITY[3:0] bits are not ‘0000’.
The input clock is disqualified if any of the above conditions is not
satisfied.
In summary, the selected input clock can be switched by:
External Fast selection;
Forced selection;
Revertive switch;
Non-Revertive switch.
3.8.2.1
Revertive Switch
In Revertive switch, the selected input clock is switched when
another qualified input clock with a higher priority than the current
selected input clock is available.
The selected input clock is switched if any of the following is satis-
fied:
The selected input clock is disqualified;
Another qualified input clock with a higher priority than the
selected input clock is available.
A qualified input clock with the higher priority is selected by revertive
switch. If more than one qualified input clock is available and has the
same priority, the input clock with the smaller ‘n’ is selected. See Table 8
for the ‘n’ assigned to each input clock.
3.8.2.2
Non-Revertive Switch
In Non-Revertive switch, the T0 selected input clock is not switched
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the higher priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smaller ‘n’ is selected. See Table 8 for the ‘n’ assigned to
each input clock.
3.8.3
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
The
selected
input
clock
is
indicated
by
the
CURRENTLY_SELECTED_INPUT[3:0] bits.
The qualified input clocks with the two highest priorities are indicated
by
the
HIGHEST_PRIORITY_VALIDATED[3:0]
bits
and
the
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] bits respectively. If
more than one input clock has the same priority, the input clock with the
smaller ‘n’ is indicated by the HIGHEST_PRIORITY_VALIDATED[3:0]
bits. See Table 8 for the ‘n’ assigned to the input clock.
When the device is configured in Automatic selection and Revertive
switch
is
enabled,
the
input
clock
indicated
by
the
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi-
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B4X-IU | CONVERTER MOD DC/DC 5.2V 200W |
| M83723/72R1404N | CONN RCPT 4POS WALL MT W/PINS |
| VI-B3W-IU | CONVERTER MOD DC/DC 5.5V 200W |
| VI-B3V-IU | CONVERTER MOD DC/DC 5.8V 200W |
| VI-B3T-IU | CONVERTER MOD DC/DC 6.5V 200W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3202NLGBLANK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V3255 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255_08 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DKG | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。