參數(shù)資料
型號： IDT82P2828BH
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 83/154頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 28+1CH 640-PBGA
標(biāo)準(zhǔn)包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2828BH
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
34
February 6, 2009
3.2.7
RECEIVER POWER DOWN
Set the R_OFF bit (b5, RCF0,...) to ‘1’ will power down the corre-
sponding receiver.
In this way, the corresponding receive circuit is turned off and the
RTIPn/RRINGn pins are forced to High-Z state. The pins on receive
system interface (including RDn/RDPn, RDNn/RMFn, RCLKn/RMFn)
will be in High-Z state if the RHZ bit (b6, RCF0,...) is ‘1’ or in low level if
the RHZ bit (b6, RCF0,...) is ‘0’.
After clearing the R_OFF bit (b5, RCF0,...), it will take 1 ms for the
receiver to achieve steady state, i.e., to return to the previous configura-
tion and performance.
3.3
TRANSMIT PATH
3.3.1
TRANSMIT SYSTEM INTERFACE
The data from the system side is input to the device in three modes:
Single Rail NRZ Format mode, Dual Rail NRZ Format mode and Dual
Rail RZ Format mode, as selected by the T_MD[1:0] bits (b1~0,
If data is input on TDn in NRZ format and a 1.544 MHz (in T1/J1
mode) or 2.048 MHz (in E1 mode) clock is input on TCLKn, the transmit
system interface is in Single Rail NRZ Format mode. In this mode, the
data is encoded and sampled on the active edge of TCLKn. TMFn is
updated on the active edge of TCLKn and can be selected to indicate
PRBS/ARB, SAIS, TOC, TLOS or SEXZ. Refer to Section 3.5.7.2 TMFn
Indication for the description of TMFn.
If data is input on TDPn and TDNn in NRZ format and a 1.544 MHz
(in T1/J1 mode) or 2.048 MHz (in E1 mode) clock is input on TCLKn, the
transmit system interface is in Dual Rail NRZ Format mode. In this
mode, the data is pre-encoded and sampled on the active edge of
TCLKn.
If data is input on TDPn and TDNn in RZ format and no transmit
clock is input, the transmit system interface is in Dual Rail RZ Format
mode. In this mode, the data is pre-encoded. TMFn can be selected to
indicate PRBS/ARB, SAIS, TOC, TLOS, SEXZ, SBPV, SEXZ + SBPV or
SLOS. Refer to Section 3.5.7.2 TMFn Indication for the description of
TMFn. The Tx Clock Recovery block is used to recover the clock signal
from the data input on TDPn and TDNn. Refer to Section 3.3.2 Tx Clock
Table-4 summarizes the multiplex pin used in different transmit
system interface.
相關(guān)PDF資料
PDF描述
IDT723624L12PF IC FIFO SYNC 256X36X2 128QFP
MS27473P22A35P CONN PLUG 100POS STRAIGHT W/PINS
MS27499E14A5S CONN RCPT 5POS BOX MNT W/SCKT
IDT723622L12PF IC FIFO SYNC 256X36X2 120QFP
MAX1108CUB+ IC ADC 8BIT LP 10-UMAX
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82P2828BHG 功能描述:IC LIU T1/J1/E1 28+1CH 640-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82P2916 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit
IDT82P2916BFG 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
IDT82P2916BFG8 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA
IDT82P5088 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*