參數(shù)資料
型號： IDT82P2828BH
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 120/154頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 28+1CH 640-PBGA
標準包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應商設備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2828BH
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
68
February 6, 2009
3.7
INTERRUPT SUMMARY
There are altogether 20 kinds of interrupt sources as listed in Table-
25. Among them, No.1 to No.19 are per-channel interrupt sources, while
No. 20 is a global interrupt source.
For interrupt sources from No.1 to No.10, the occurrence of the event
will cause the corresponding Status bit to be set to ‘1’. And selected by
the Interrupt Trigger Edges Select bit, either a transition from ‘0’ to ‘1’ or
any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ of the Status bit will cause
the Interrupt Status bit to be set to ‘1’, which indicates the occurrence of
an interrupt event.
For interrupt sources from No.11 to No.20, the occurrence of the
event will cause the corresponding Interrupt Status Bit to be set to ‘1’.
All the interrupt can be masked by the GLB_IM bit (b1, GCF) globally
or by the corresponding interrupt mask bit individually. For all the inter-
rupt sources, if not masked, the occurrence of the interrupt event will
trigger an interrupt indicated by the INT pin. For per-channel interrupt
sources, if not masked, the occurrence of the interrupt event will also
cause the corresponding INT_CHn bit (INTCH1~4) to be set ‘1’.
An interrupt event is cleared by writing ‘1’ to the corresponding Inter-
rupt Status bit. The INT_CHn bit (INTCH1~4) will not be cleared until all
the interrupts in the corresponding channel are acknowledged. The INT
pin will be inactive until all the interrupts are acknowledged. Refer to
Figure-45 for interrupt service flow.
Table-25 Interrupt Summary
No.
Interrupt Source
Status Bit
Interrupt Trigger Edges
Select Bit
Interrupt Status Bit
Interrupt Mask Bit
1
TCLKn is missing.
TCKLOS_S (b3,
TCKLOS_IES (b3,
INTES,...)
TCKLOS_IS (b3,
INTS0,...)
TCKLOS_IM (b3,
INTM0,...)
2
LLOS is detected.
LLOS_S (b0, STAT0,...)
LOS_IES (b1, INTES,...)
LLOS_IS (b0, INTS0,...)
LLOS_IM (b0, INTM0,...)
3
SLOS is detected.
SLOS_S (b1, STAT0,...)
LOS_IES (b1, INTES,...)
SLOS _IS (b1, INTS0,...)
SLOS_IM (b1, INTM0,...)
4
TLOS is detected.
TLOS_S (b2, STAT0,...)
TLOS_IES (b2, INTES,...)
TLOS_IS (b2, INTS0,...)
TLOS_IM (b2, INTM0,...)
5
LAIS is detected.
LAIS_S (b6, STAT1,...)
AIS_IES (b6, INTES,...)
LAIS_IS (b6, INTS1,...)
LAIS_IM (b6, INTM1,...)
6
SAIS is detected.
SAIS_S (b7, STAT1,...)
AIS_IES (b6, INTES,...)
SAIS_IS (b7, INTS1,...)
SAIS_IM (b7, INTM1,...)
7
TOC is detected.
TOC_S (b4, STAT0,...)
TOC_IES (b4, INTES,...)
TOC_IS (b4, INTS0,...)
TOC_IM (b4, INTM0,...)
8
The PRBS/ARB pattern is detected syn-
chronized.
PA_S (b5, STAT1,...)
PA_IES (b5, INTES,...)
PA_IS (b5, INTS1,...)
PA_IM (b5, INTM1,...)
9
Activate IB code is detected.
IBA_S (b1, STAT1,...)
IB_IES (b0, INTES,...)
IBA_IS (b1, INTS1,...)
IBA_IM (b1, INTM1,...)
10
Deactivate IB code is detected.
IBD_S (b0, STAT1,...)
IB_IES (b0, INTES,...)
IBD_IS (b0, INTS1,...)
IBD_IM (b0, INTM1,...)
11
The FIFO of the RJA is overflow or
underflow.
-
RJA_IS (b5, INTS0,...)
RJA_IM (b5, INTM0,...)
12
The FIFO of the TJA is overflow or
underflow.
-
TJA_IS (b6, INTS0,...)
TJA_IM (b6, INTM0,...)
13
Waveform amplitude is overflow.
-
DAC_IS (b7, INTS0,...)
DAC_IM (b7, INTM0,...)
14
SBPV is detected.
-
SBPV_IS (b5, INTS2,...)
SBPV_IM (b5, INTM2,...)
15
LBPV is detected.
-
LBPV_IS (b4, INTS2,...)
LBPV_IM (b4, INTM2,...)
16
SEXZ is detected.
-
SEXZ_IS (b3, INTS2,...)
SEXZ_IM (b3, INTM2,...)
17
LEXZ is detected.
-
LEXZ_IS (b2, INTS2,...)
LEXZ_IM (b2, INTM2,...)
18
PRBS/ARB error is detected.
-
ERR_IS (b1, INTS2,...)
ERR_IM (b1, INTM2,...)
19
The ERRCH and ERRCL registers are
overflowed.
-
CNTOV_IS (b0, INTS2,...) CNTOV_IM (b0, INTM2,...)
20
One second time is over.
-
TMOV_IS (b0, INTTM)
TMOV_IM (b0, GCF)
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