IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM WITH BUS MATCHI" /> 
            


    
    



    

    
  
    
    
    
    
    
      
    
    
  
    
  
  

    





    


    
 
 




 
 


    

    
    


    參數(shù)資料
    

    


    


    
型號：
IDT72V3666L10PF

    

    
廠商：
IDT, Integrated Device Technology Inc

    

    
文件頁數(shù)：
35/39頁

    

    
文件大?。?/td>
0K

    

    
描述：
IC FIFO SYNC 8192X36 10NS 128QFP

    

    
標(biāo)準(zhǔn)包裝：
36

    

    
系列：
72V

    

    
功能：
異步
    		

    

    
存儲容量：
288K（8K x 36）
    		

    

    
數(shù)據(jù)速率：
100MHz
    		

    

    
訪問時間：
10ns
    		

    

    
電源電壓：
3.15 V ~ 3.45 V
    		

    

    
工作溫度：
0°C ~ 70°C
    		

    

    
安裝類型：
表面貼裝
    		

    

    
封裝/外殼：
128-LQFP
    		

    

    
供應(yīng)商設(shè)備封裝：
128-TQFP（14x20）
    		

    

    
包裝：
托盤
    		

    

    
其它名稱：
72V3666L10PF
    		

    

    

    

	
    
    
    

    
    
	
    5
    COMMERCIALTEMPERATURERANGE
    IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
    WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
    PIN DESCRIPTIONS (CONTINUED)
    Symbol
    Name
    I/O
    Description
    FS0/SD
    Flag Offset Select 0/
    I
    FS1/
    SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,
    Serial Data
    FS1/
    SEN and FS0/SD, together with FS2, select the flag offset programming method. Three Offset register
    programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024),
    FS1/
    SEN
    Flag Offset Select 1/
    I
    parallel load from Port A, and serial load.
    Serial Enable
    When serial load is selected for flag Offset register programming, FS1/
    SEN is used as an enable synchronous to
    FS2(1)
    Flag Offset Select 2
    I
    the LOW-to-HIGH transition of CLKA. When FS1/
    SEN is LOW, a rising edge on CLKA load the bit present on
    FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 44 for the
    72V3656, 48 for the 72V3666, and 52 for the 72V3676. The first bit write stores the Y-register (Y1) MSB and the
    last bit write stores the X-register (X2) LSB.
    LOOP
    LoopbackSelect
    I
    This pin selects the loopback feature for Port A. During Loopback data from FIFO2 will be directed to the input of
    FIFO1. to initiate a Loop the
    LOOP pin must be held LOW and the ENA pin must be HIGH.
    MBA
    Port A Mailbox
    I
    A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
    Select
    outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects
    FIFO2 output-register data for output.
    MBB
    Port B Mailbox
    I
    A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
    Select
    active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output
    register data for output.
    MBC
    Port C Mailbox
    I
    A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
    Select
    Master Reset.
    MBF1
    Mail1 Register
    O
    MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
    Flag
    register are inhibited while
    MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
    Port B read is selected and MBB is HIGH.
    MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
    MBF2
    Mail2 Register
    O
    MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2
    Flag
    register are inhibited while
    MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a
    Port A read is selected and MBA is HIGH.
    MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
    MRS1
    Master Reset
    I
    A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
    output register to all zeroes. A LOW-to-HIGH transition on
    MRS1 selects the programming method (serial or
    parallel) and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and
    C for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
    transitions of CLKB must occur while
    MRS1 is LOW.
    MRS2
    Master Reset
    I
    A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
    output register to all zeroes. A LOW-to-HIGH transition on
    MRS2,toggledsimultaneouslywithMRS1, selects
    the programming method (serial or parallel) and one of the five flag default offsets for FIFO2. Four LOW-to-HIGH
    transitions of CLKA and four LOW-to-HIGH transitions of CLKC must occur while
    MRS2 is LOW.
    PRS1/
    PartialReset/
    I
    This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
    RT1
    RetransmitFIFO1
    is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read and write
    pointerstothefirstlocationofmemoryandsetsthePortBoutputregistertoallzeroes.DuringPartialReset,thecurrently
    selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
    all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read pointer only to
    thefirstmemorylocation.
    PRS2/
    PartialReset/
    I
    This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
    RT2
    RetransmitFIFO2
    is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read and write
    selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
    all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer only to
    thefirstmemorylocation.
    RENB
    Port B Read Enable
    I
    RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
    RTM
    RetransmitMode
    I
    This pin is used in conjunction with the
    RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on FIFO1
    or FIFO2 respectively.
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

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IDT72V3666L10PF8
功能描述:IC FIFO SYNC 8192X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF

    

    
IDT72V3666L15PF
功能描述:IC FIFO SYNC 8192X36 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433

    

    
IDT72V3666L15PF8
功能描述:IC FIFO SYNC 8192X36 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF

    

    
IDT72V3670L10PF
功能描述:IC FIFO SYNC II 36BIT 128-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984

    

    
IDT72V3670L10PF8
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