IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM WITH BUS MATCH" />
參數(shù)資料
型號(hào): IDT72V3666L10PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 27/39頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 8192X36 10NS 128QFP
標(biāo)準(zhǔn)包裝: 36
系列: 72V
功能: 異步
存儲(chǔ)容量: 288K(8K x 36)
數(shù)據(jù)速率: 100MHz
訪問時(shí)間: 10ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 72V3666L10PF
33
COMMERCIALTEMPERATURERANGE
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for
AFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then
AFC may transition HIGH one CLKC cycle later than shown.
2. FIFO2 write (MBC = LOW), FIFO2 read (
CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3656, 4,096 for the IDT72V3666, 8,192 for the IDT72V3676.
4. Port C size is word or byte,
AFC is set LOW by the last word or byte write of the long word, respectively.
Figure 27. Timing for
AFC
AFC when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
Figure 25. Timing for
AEA
AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
Figure 26. Timing for
AFA
AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for
AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then
AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (MBC = LOW), FIFO2 read (
CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for
AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then
AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3656, 4,096 for the IDT72V3666, 8,192 for the IDT72V3676.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
AEA
CLKC
ENA
4665 drw 26
WENC
CLKA
2
1
tENS2
tENH
tSKEW2
tPAE
tENS2
tENH
(X2+1) Words in FIFO2
X2 Words in FIFO2
(1)
AFA
CLKA
RENB
4665 drw 27
ENA
CLKB
12
tSKEW2
tENS2
tENH
tPAF
tENS2
tENH
tPAF
[D-(Y1+1)] Words in FIFO1
(D-Y1) Words in FIFO1
(1)
AFC
CLKC
ENA
4665 drw 28
WENC
CLKA
12
tSKEW2
tENS2
tENH
tPAF
tENS2
tENH
tPAF
[D-(Y2+1)] Words in FIFO2
(D-Y2) Words in FIFO2
(1)
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