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參數(shù)資料
| 型號(hào)： | IDT72V2111L15PFGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 21/27頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 3.3V 15NS 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲(chǔ)容量： | 4.6K（512 x 9） |
| 訪問(wèn)時(shí)間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（14x14） |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 1255 (CN2011-ZH PDF) |
| 其它名稱(chēng)： | 72V2111L15PFGI 800-1512 |
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3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
Figure 1. Block Diagram of Single 262,144 x 9 and 524,288 x 9 Synchronous FIFO
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. (See Table I and Table II.) Programmable offsets determine the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
defaultoffsetsettingsarealsoprovided,sothat
PAEcanbesettoswitchat127
or 1,023 locations from the empty boundary and the
PAFthresholdcanbeset
at 127 or 1,023 locations from the full boundary. These choices are made with
the
LD pin during Master Reset.
For serial programming,
SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming,
WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via Dn.
REN together with LD on each
rising edge of RCLK can be used to read the offsets in parallel from Qn
regardless of whether serial or parallel offset loading has been selected.
During Master Reset (
MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The
LDpinselectseitherapartialflagdefault
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023
with serial programming. The flags are updated according to the timing mode
anddefaultoffsetsselected.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect.
PRS is useful for resetting a device in mid-
operation, when reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO. A LOW
on the
RT input during a rising RCLK edge initiates a retransmit operation
by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V2101/72V2111 are fabricated using IDT’s high speed submi-
cron CMOS technology.
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72V2101
72V2111
PARTIAL RESET (PRS)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (RT)
4669 drw 03
HALF FULL FLAG (HF)
SERIAL ENABLE(SEN)
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT72V2111L15PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 512X9 15NS 64QFP |
| IDT72V2111L15PFI | 功能描述:IC FIFO SS 512X9 15NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433 |
| IDT72V2111L15PFI8 | 功能描述:IC FIFO SS 512X9 15NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433 |
| IDT72V2111L20PF | 功能描述:IC FIFO SS 512X9 20NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433 |
| IDT72V2111L20PF8 | 功能描述:IC FIFO SS 512X9 20NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433 |
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