- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9890 > IDT72T7295L5BB (IDT, Integrated Device Technology Inc)IC FIFO 32768X72 5NS 324-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT72T7295L5BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 51/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 32768X72 5NS 324-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 訪問時(shí)間： | 5ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA |
| 供應(yīng)商設(shè)備封裝： | 324-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T7295L5BB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當(dāng)前第51頁第52頁第53頁
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O TYPE
Description
PAE
Programmable
HSTL-LVTTL
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the
Almost-EmptyFlag
OUTPUT
Empty Offset register.
PAE goes HIGH if the number of words in the FIFO memory is greater than or equal
tooffsetn.
PAF
Programmable
HSTL-LVTTL
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
Almost-FullFlag
OUTPUT
the Full Offset register.
PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthanorequal
tom.
PFM(1)
Programmable
LVTTL
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
Flag Mode
INPUT
PFM will select Synchronous Programmable flag timing mode.
PRS
PartialReset
HSTL-LVTTL
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
INPUT
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
Q0–Q71
DataOutputs
HSTL-LVTTL Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, any unused output pins should not
OUTPUT
be connected. Outputs are not 3.3V tolerant regardless of the state of
OE and RCS.
RCLK/
Read Clock/
HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by
REN,therisingedgeofRCLK
RD
Read Strobe
INPUT
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.If
LDisLOW,thevaluesloaded
into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has
been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner.
REN should be
tiedLOW.
RCS
Read Chip Select
HSTL-LVTTL
RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During
INPUT
aMasterResetorPartialResetthe
RCSinputisdon’tcare,ifOEisLOWthedataoutputswillbeLow-Impedance
regardless of
RCS.
REN
Read Enable
HSTL-LVTTL If Synchronous operation of the read port has been selected,
REN enables RCLK for reading data from the
INPUT
FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the
REN
input should be tied LOW.
RHSTL(1) Read Port HSTL
LVTTL
This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
Select
INPUT
required, this input must be tied HIGH. Otherwise it should be tied LOW.
RT
Retransmit
HSTL-LVTTL
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to
INPUT
HIGH in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode or
programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to
the‘mark’location.
SCLK
Serial Clock
HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT
SEN is enabled.
SEN
Serial Enable
HSTL-LVTTL
SENenablesserialloadingofprogrammableflagoffsets.
INPUT
SHSTL
System HSTL
LVTTL
All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select
INPUT
TCK(2)
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
INPUT
of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(2)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Input
INPUT
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(2)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Output
OUTPUT
test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID
Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and
SHIFT-IR controller states.
TMS(2)
JTAG Mode
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
Select
INPUT
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS27466T21F16S | CONN RCPT 16POS WALL MT W/SCKT |
| MS27474E14A5P | CONN RCPT 5POS JAM NUT W/PINS |
| IDT72T72115L10BB | IC FIFO 131072X72 10NS 324-BGA |
| D38999/20WF11SN | CONN RCPT 11POS WALL MNT W/SCKT |
| MS3101E20-8S | CONN RCPT 6POS FREE HNG W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T7295L6-7BB | 功能描述:IC FIFO 32768X72 6-7NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V01L15J | 功能描述:IC ASYNCH 512X9 15NS 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72V01L15J8 | 功能描述:IC ASYNCH 512X9 15NS 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72V01L15JG | 功能描述:IC ASYNCH 512X9 15NS 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72V01L15JG8 | 功能描述:IC ASYNCH 512X9 15NS 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。