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參數(shù)資料
| 型號(hào)： | IDT70125S45J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 2K X 9 DUAL-PORT SRAM, 45 ns, PQCC52 |
| 封裝： | 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | IDT70125S45J |
6.10
11
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT70121/125 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70121/125 has an
automatic power down feature controlled by
CE
. The
CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(
CE
high). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
INT
L
) is asserted when the right port
writes to memory location 7FE (HEX), where a write is defined
as the
CE
= R/
W
= V
IL
per the Truth Table. The left port clears
the interrupt by access address location 7FE access when
CE
R
=
OE
R =
V
IL,
R/
W
is a "Don't Care". Likewise, the right port
interrupt flag (
INT
R
) is asserted when the left port writes to
memory location 7FF (HEX) and to clear the interrupt flag
(
INT
R
), the right port must access the memory location 7FF.
The message (9 bits) at 7FE or 7FF is user-defined, since it is
an addressable SRAM location. If the interrupt function is not
used, address locations 7FE and 7FF are not used as mail
boxes, but as part of the random access memory. Refer to
Table I for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by using the IDT70125
(SLAVE). In the IDT70125, the busy pin operates solely as a
write inhibit input pin. Normal operation can be programmed
by tying the
BUSY
pins high. Once in slave mode the
BUSY
pin
operates solely as a write inhibit input pin. Normal operation
can be programmed by tying the
BUSY
pins high. If desired,
unintended write operations can be prevented to a port by
tying the busy pin for that port low.
The busy outputs on the IDT70121/125 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70121/125 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70121 RAM the busy pin
is an output of the part, and the busy pin is an input of the
IDT70125 as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
MASTER
Dual Port
BUSY
L
BUSY
R
CE
MASTER
Dual Port
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
D
IDT70121
IDT70121
IDT70125
IDT70125
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70121 (Master) and IDT70125 (Slave) RAMs.
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/
W
signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70125S45JG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125S45JGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125S45L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70125S45L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70125S55J | 功能描述:IC SRAM 18KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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