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參數(shù)資料
| 型號(hào)： | IDT70125L45J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 2K X 9 DUAL-PORT SRAM, 45 ns, PQCC52 |
| 封裝： | 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 168K |
| 代理商： | IDT70125L45J |
6.10
7
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(6)
70121X25
70125X25
Min. Max. Min. Max. Min. Max. Min. Max
.
Unit
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Symbol
Busy Timing
(For Master IDT70121 Only)
t
BAA
BUSY
Access Time from Address
t
BDA
BUSY
Disable Time from Address
t
BAC
BUSY
Access Time from Chip Enable
t
BDC
BUSY
Disable Time from Chip Enable
t
WDD
Write Pulse to Data Delay
(1)
t
DDD
Write Data Valid to Read Data Delay
(1)
t
APS
Arbitration Priority Set-up Time
(2)
t
BDD
BUSY
Disable to Valid Data
(3)
t
WH
Write Hold After
BUSY
(5)
Busy Timing
(For Slave IDT70125 Only)
t
WB
Write to
BUSY
Input
(4)
t
WH
Write Hold After
BUSY
(5)
t
WDD
Write Pulse to Data Delay
(1)
t
DDD
Write Data Valid to Read Data Delay
(1)
Parameter
—
—
—
—
—
—
5
—
15
20
20
20
20
50
35
—
30
—
—
—
—
—
—
—
5
—
20
20
20
20
20
60
45
—
30
—
—
—
—
—
—
—
5
—
20
20
20
20
20
70
55
—
35
—
—
—
—
—
—
—
5
—
20
30
30
30
30
80
65
—
45
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
15
—
—
—
—
50
35
0
20
—
—
—
—
60
45
0
20
—
—
—
—
70
55
0
20
—
—
—
—
80
65
ns
ns
ns
ns
NOTES
:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and
BUSY
“.
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. “X” in part numbers indicates power rating (S or L).
2654 tbl 10
NOTES:
1. R/
W
or
CE
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
= V
IL
and a R/
W
= V
IL
3. t
WR
is measured from the earlier of
CE
or R/
W
going High to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t
WP
.
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
CONTROLLED TIMING
(1,5)
CE
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
2654 drw 08
(6)
(2)
(3)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70125L45JG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125L45JGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125L45L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70125L45L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70125L55J | 功能描述:IC SRAM 18KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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