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參數(shù)資料
| 型號(hào)： | IDT70125L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Low-Power JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
| 中文描述： | 高速2K × 9雙端口靜態(tài)RAM繁忙 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 168K |
| 代理商： | IDT70125L |
Integrated Device Technology, Inc.
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM WITH BUSY & INTERRUPT
IDT70121S/L
IDT70125S/L
FEATURES:
High-speed access
– Commercial: 25/35/45/55ns (max.)
Low-power operation
– IDT70121/70125S
Active: 500mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 500mW (typ.)
Standby: 1mW (typ.)
Fully asychronous operation from either port
MASTER IDT70121 easily expands data bus width to 18
bits or more using SLAVE IDT70125 chip
On-chip port arbitration logic (IDT70121 only)
BUSY
output flag on Master;
BUSY
input on Slave
INT
flag for port-to-port communication
Battery backup operation—2V data retention
TTL-compatible, signal 5V (
±
10%) power supply
Available in 52-pin PLCC
Industrial temperature range (–40
°
C to +85
°
C) is avail-
able, tested to military electrical specifications
COMMERCIAL TEMPERATURE RANGE
OCTOBER 1996
1996 Integrated Device Technology, Inc.
DSC-2654/4
1
NOTES:
1. 70121 (MASTER):
BUSY
is non-tri-
stated push-pull
output.
70125 (SLAVE):
BUSY
is input.
2.
INT
is totem-pole
output.
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port
RAM together with the IDT70125 “SLAVE” Dual-Port in 18-
bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn-
chronous access for reads or writes to any location in memory.
An automatic power-down feature, controlled by
CE
, permits
the on-chip circuitry of each port to enter a very low standby
power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to
allow for Data/Control and parity bits at the user’s option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
W
L
CE
L
OE
L
BUSY
L
A
10L
A
0L
2654 drw 01
I/O
0L
- I/O
8L
CE
L
OE
L
R/
W
L
INT
L
BUSY
R
I/O
0R
-I/O
8R
A
11R
A
0R
INT
R
CE
R
OE
R
R/
W
R
(2)
(1,2)
(1,2)
(2)
R/
W
R
CE
R
OE
R
11
11
6.10
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70125L25J | 功能描述:IC SRAM 18KBIT 25NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT70125L25J8 | 功能描述:IC SRAM 18KBIT 25NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT70125L25JG | 功能描述:IC SRAM 18KBIT 25NS 52PLCC RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT70125L25JG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 18KBIT 25NS 52PLCC |
| IDT70125L25JGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
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