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    參數(shù)資料
    

    


    


    
型號(hào)：
IDT70125L45J

    

    
廠商：
INTEGRATED DEVICE TECHNOLOGY INC

    

    
元件分類：
DRAM

    

    
英文描述：
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

    

    
中文描述：
2K X 9 DUAL-PORT SRAM, 45 ns, PQCC52

    

    
封裝：
0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52

    

    
文件頁(yè)數(shù)：
6/12頁(yè)

    

    
文件大小：
168K

    

    
代理商：
IDT70125L45J


    

    

    

	
    
    
    

    
    
	
    6.10
    6
    IDT 70121/70125S/L
    HIGH-SPEED 2K x  9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
    COMMERCIAL TEMPERATURE RANGE
    AC ELECTRICAL CHARACTERISTICS OVER THE
    OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
    (4)
    70121X25
    70125X25
    Min. Max. Min. Max. Min. Max. Min. Max
    .
     Unit
    70121X35
    70125X35
    70121X45
    70125X45
    70121X55
    70125X55
    Symbol
    Write Cycle
    t
    WC
    t
    EW
    t
    AW
    t
    AS
    t
    WP
    t
    WR
    t
    DW
    t
    HZ
    t
    DH
    t
    WZ
    t
    OW
    Parameter
    Write Cycle Time
    (3)
    Chip Enable to End-of-Write
    Address Valid to End-of-Write
    Address Set-up Time
    Write Pulse Width
    (6)
    Write Recovery Time
    Data Valid to End-of-Write
    Output High-Z Time
    (1,2)
    Data Hold Time
    (5)
    Write Enabled to Output in High-Z
    (1,2)
    Output Active from End-of-Write
    (1,2)
    25
    20
    20
    0
    20
    0
    12
    —
    0
    —
    0
    —
    —
    —
    —
    —
    —
    —
    10
    —
    10
    —
    35
    30
    30
    0
    30
    0
    20
    —
    0
    —
    0
    —
    —
    —
    —
    —
    —
    —
    15
    —
    15
    —
    45
    35
    35
    0
    35
    0
    20
    —
    0
    —
    0
    —
    —
    —
    —
    —
    —
    —
    20
    —
    20
    —
    55
    40
    40
    0
    40
    0
    20
    —
    0
    —
    0
    —
    —
    —
    —
    —
    —
    —
    30
    —
    30
    —
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    NOTES:
    1. Transition is measured 
    ±
    500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
    2. This parameter guaranteed by device characterization, but is not production tested.
    3. For MASTER/SLAVE combination, t
    WC
     = t
    BAA
     + t
    WP,
     since R/
    W
    = V
    IL
      must occur after t
    BAA
     .
    4. “X” in part numbers indicates power rating (S or L).
    5. The specified t
    DH 
     must be met by the device supplying write date to the RAM under all operating conditions.Although t
    DH 
    and
    t
    ow 
    values will vary over voltage
    and temperature. The actual t
    DH 
    will always be smaller than the actual t
    OW.
    6. If 
    OE
     is low during a R/
    W
     controlled write cycle, the write pulse width must be the larger of t
    WP
     or (t
    WZ
     + t
    DW
    ) to allow the I/O drivers to turn off
    data to be placed on the bus for the required t
    DW
    .  If 
    OE
     is High during a R/
    W
     controlled write cycle, this requirement does not apply and the
    write pulse can be as short as the specified t
    WP.
    2654 tbl 09
    TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
    W
     CONTROLLED TIMING
    (1,5,8)
    R/
    W
    t
    WC
    t
    HZ
    t
    AW
    t
    HZ
    t
    AS
    t
    WP
    DATA
    OUT
    t
    DW
    t
    DH
    t
    OW
    OE
    ADDRESS
    DATA
    IN
    CE
    t
    WZ
    (4)
    (4)
    t
    WR
    2654 drw 07
    (3)
    (7)
    (2)
    (6)
    (7)
    (7)
    NOTES:
    1. R/
    W
     or 
    CE
     must be High during all address transitions.
    2. A write occurs during the overlap (t
    EW
     or t
    WP
    ) of a 
    CE
     = V
    IL
     and a R/
    W
     = V
    IL
    3. t
    WR
     is measured from the earlier of 
    CE
     or R/
    W
     going High to the end of the write cycle.
    4. During this period, the I/O pins are in the output state and input signals must not be applied.
    5. If the 
    CE
     Low transition occurs simultaneously with or after the R/
    W
     Low transition, the outputs remain in the High-impedance state.
    6.   Timing depends on which enable signal (
    CE
     or R/
    W
    ) is asserted last.
    7.   This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV  from steady state
    with the Output Test Load (Figure 2).
    8. If 
    OE
     is low during a R/
    W
     controlled write cycle, the write pulse width must be the larger of t
    WP
     or (t
    WZ
     + t
    DW
    ) to allow the I/O drivers to turn off
    data to be placed on the bus for the required t
    DW
    .  If 
    OE
     is High during a R/
    W
     controlled write cycle, this requirement does not apply and the
    write pulse can be as short as the specified t
    WP
    .
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
IDT70125L45JG
 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

    

    
IDT70125L45JGI
 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

    

    
IDT70125L45L52
 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM

    

    
IDT70125L45L52B
 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM

    

    
IDT70125L55J
功能描述:IC SRAM 18KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR)

    

    
    
    
    
	
    	
    
    
     
     
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