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| 型號(hào)： | IDT7007L35PFB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 32K X 8 DUAL-PORT SRAM, 35 ns, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80 |
| 文件頁(yè)數(shù)： | 13/21頁(yè) |
| 文件大?。?/td> | 257K |
| 代理商： | IDT7007L35PFB |
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IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6,7)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
t
WP
(actual) or t
DDD
t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
Symbol
Parameter
7007X15
Com'l Only
7007X20
Com'l Only
7007X25
Com'l &
Military
Unit
Min.
Max.
Min.
Max.
Min.
Max.
BUSY
TIMING (M/
S
=V
IH
)
t
BAA
BUSY
Access Time from Address Match
____
15
____
20
____
20
ns
t
BDA
BUSY
Disable Time from Address Not Matched
____
15
____
20
____
20
ns
t
BAC
BUSY
Access Time from Chip Enable Low
____
15
____
20
____
20
ns
t
BDC
BUSY
Access Time from Chip Enable High
____
15
____
17
____
17
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
18
____
30
____
30
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
17
____
ns
BUSY
TIMING (M/
S
=V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
30
____
45
____
50
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
30
____
35
ns
2940 tbl 14a
Symbol
Parameter
7007X35
Com'l &
Military
7007X55
Com'l, Ind
& Military
Unit
Min.
Max.
Min.
Max.
BUSY
TIMING (M/
S
=V
IH
)
t
BAA
BUSY
Access Time from Address Match
____
20
____
45
ns
t
BDA
BUSY
Disable Time from Address Not Matched
____
20
____
40
ns
t
BAC
BUSY
Access Time from Chip Enable Low
____
20
____
40
ns
t
BDC
BUSY
Access Time from Chip Enable High
____
20
____
35
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
35
____
40
ns
t
WH
Write Hold After
BUSY
(5)
25
____
25
____
ns
BUSY
TIMING (M/
S
=V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
60
____
80
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
45
____
65
ns
2940 tbl 14b
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PDF描述 |
|---|---|
| IDT7007L35PFI | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L55G | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L55GB | LCD BACKLIGHT INVERTER DRIVE IC; Package: SOIC-Wide; No of Pins: 20; Container: Tape & Reel |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7007L35PFI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L45G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7007L45GB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7007L45J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7007L45PF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
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