FIN
參數(shù)資料
型號(hào)： IDT5V9885TNLGI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 2/39頁(yè)
文件大小： 0K
描述： IC CLOCK GEN PLL 500MHZ 28VFQFPN
標(biāo)準(zhǔn)包裝： 490
類型： *
PLL： 帶旁路
輸入： LVCMOS，LVTTL
輸出： LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:6
差分 - 輸入:輸出： 無/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/無
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-VFQFPN（6x6）
包裝： 托盤
其它名稱： 800-2580
10
INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Example
FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings.
Since the spread is center, the SS_OFFSET can be set to '0'. Solve for the nominal M value; keep in mind that the nominal M should be chosen to maximize
the VCO. Start with D = 1, using Eq.10 and Eq.11.
MNOM = 1200MHz / 25MHz = 48
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we have the nominal M value, we can determine TSSC and NSSC by using Eq.12.
Nssc * Tssc = 25MHz / (33KHz * 4) = 190
However, using Eq. 7 and Eq.8, we find that the closest value is when TSSC = 14 and NSSC = 6. Keep in mind to maximize the number of samples used
to enhance the profile of the spread spectrum waveform.
Tssc = 14 + 2 = 16
Nssc = 6 * 2 = 12
Nssc * Tssc = 192
Use Eq.14 to determine the value of the sigma-delta-encoded samples.
±2% = Σ * 100
64 * 48
Σ = 61.44
Either round up or down to the nearest integer value. Therefore, we end up with 61 or 62 for sigma-delta-encoded samples. Since the sigma-delta-encoded
samples must not exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within the limits. It is the discretion of the user to define the shape of the profile that
is better suited for the intended application.
Using Eq.14 again, the actual spread for the sigma-delta-encoded samples of 61 and 62 are ±1.99% and ±2.02%, respectively.
Use Eq.10 to determine if the X2 bit needs to be set;
Amplitude = 48 * (1.99 or 2.02) / 100 = 0.48 < 1
2
Therefore, the X2 = '0 '. The dither bit is left to the discretion of the user.
The example above was of a center spread using spread spectrum. For down spread, the nominal M value can be set one integer value lower to 43.
Note that the 5V9885T should not be programmed with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator.
ThePLLloopbandwidthmustbeatleast10xthemodulationfrequencyalongwithhigherdamping(larger ωuz)topreventthespreadspectrumfrombeingfiltered
and reduce extraneous noise. Refer to the LOOP FILTER section for more detail on ωuz. The A[3:0] must be used for spread spectrum, even if the total multiplier
value is an even integer.
FRACTIONAL DIVIDER
There is the option for the feedback-divider to be programmed as a fractional divider for only PLL0 and PLL. By setting TSSC > '0' and SD bits to '0', the
SS_OFFSET bits would determine the fractional divide value. See the SPREAD SPECTRUM GENERATION section for more details on the TSSC, SD, and
SS_OFFSET bits. The following equation governs how the fractional divide value is set.
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] *1/64
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IDT5V9885TNLGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN
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