參數(shù)資料
型號(hào): IDT5V9352PRI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
中文描述: PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: TQFP-32
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 81K
代理商: IDT5V9352PRI
5
INDUSTRIAL TEMPERATURE RANGE
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
Symbol
t
R,
t
F
Characteristic
Test Conditions
Min.
0.1
Typ.
Max.
1
200
200
100
100
400
200
100
66.6
50
33.3
53
+150
+150
8
Unit
ns
Output Rise/Fall Time
0.55V to 2.4V
All Outputs, any frequency
within Q
A
output bank
within Q
B
output bank
within Q
C
output bank
t
SK(O)
Output to Output Skew
ps
f
VCO
PLL VCO Lock Range
(2)
200
100
50
33.3
25
16.67
47
-200
-50
MHz
÷
2 output
÷
4 output
÷
6 output
÷
8 output
÷
12 output
f
MAX
MaximumOutput Frequency
MHz
t
PW
t
PD
Output Duty Cycle
REFCLK to FBIN Delay
PLL Locked
Output Disable Time
MR/
OE
(LOW-HIGH) to any Q
Output Enable Time
MR/
OE
(HIGH-LOW) to any Q
50
%
ps
f
REF
< 40MHz
f
REF
> 40MHz, PLL locked
t
PLZ
t
PHZ
t
PZL
t
PZH
ns
10
ns
Output frequencies mxed
Outputs in any
÷
4 and
÷
6 combination
All outputs same frequency
Output frequencies mxed
Outputs in any
÷
4 and
÷
6 combination
All outputs same frequency
÷
4 feedback divider RMS (1
σ
)
÷
6 feedback divider RMS (1
σ
)
÷
8 feedback divider RMS (1
σ
)
÷
12 feedback divider RMS (1
σ
)
÷
4 feedback
÷
6 feedback
÷
8 feedback
÷
12 feedback
400
250
100
200
150
75
t
J
Cycle-to-Cycle Jitter
ps
t
J(PER)
Period Jitter
ps
15
20
t
J(
φ
)
I/O Phase Jitter
ps
18-20
25
3 - 10
1.5 - 6
1 - 3.5
0.5 - 2
BW
PLL Closed Loop Bandwidth
MHz
t
LOCK
MaximumPLL Lock Time
10
ms
AC ELECTRICAL CHARACTERISTICS
(1)
T
A
= –40°C to +85°C, V
CC
= 3.3V ± 5%
NOTES:
1. AC characteristics apply for parallel output termnation of 50
to V
TT
.
2. The input frequency on CCLK must match the VCO frequency range divided by the feedback divide ratio FB: freq. = fvco
÷
FB.
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