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參數(shù)資料
| 型號： | IDT5V551DCI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER 1:4 160MHZ 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Clock Distibution and Generation 1.0 |
| 產(chǎn)品變化通告： | Product Discontinuation 13/May/2009 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 輸入： | LVTTL |
| 輸出： | LVTTL |
| 頻率 - 最大： | 160MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 5V551DCI8 |
3
IDT5V551
1:4CLOCKBUFFER
INDUSTRIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FollowingConditionsApplyUnlessOtherwiseSpecified
TA = -40°C to +85°C, VDD = 3.3V ± 5%
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
FIN
InputFrequency
0
—
160
MHz
FOUT
OutputFrequency(1)
15pFload
—
160
MHz
tOR
Output Clock Rise Time
0.8V to 2V
—
1.5
ns
tOF
OutputClockFallTime
2V to 0.8V
—
1.5
ns
tPD
PropagationDelay(2)
135MHz
2
4
8
ns
tSK(O)
OutputtoOutputSkew(3)
Rising edges at VDD/2
—
250
ps
NOTES:
1. With external series resistor of 33
positioned close to each output pin.
2. With rail-to-rail input clock.
3. Between any two outputs with equal loading.
4. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
TEST CONDITIONS
Symbol
VDD = 3.3V ± 5%
Unit
CL
15
pF
RT
ZOUT of pulse generator
RL
33
tR/tF
1 (0V to 3V or 3V to 0V)
ns
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to the ZOUT of the pulse generator.
tR/tF = Rise/Fall time of the input stimulus from the pulse generator.
D.U.T.
Pulse
Generator
VIN
VOUT
VDD
RT
CL
RL
TEST CIRCUIT
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