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參數(shù)資料
| 型號(hào)： | IDT5V551DCI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER 1:4 160MHZ 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Clock Distibution and Generation 1.0 |
| 產(chǎn)品變化通告： | Product Discontinuation 13/May/2009 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 輸入： | LVTTL |
| 輸出： | LVTTL |
| 頻率 - 最大： | 160MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 5V551DCI8 |
1
IDT5V551
1:4CLOCKBUFFER
INDUSTRIALTEMPERATURERANGE
MARCH 2010
2006 Integrated Device Technology, Inc.
DSC - 6567/10
c
IDT5V551
INDUSTRIAL TEMPERATURE RANGE
1:4 CLOCK BUFFER
FUNCTIONAL BLOCK DIAGRAM
ICLK
Q1
Q2
Q3
Q4
OUTPUT ENABLE
PIN CONFIGURATION
Q1
Q3
Q4
OE
ICLK
Q2
VDD
GND
1
2
3
4
5
6
7
8
SOIC
TOP VIEW
FEATURES:
Advanced, low power CMOS process
5V tolerant inputs
Low skew outputs (<250ps)
Input/Output frequency up to 160MHz
Non-inverting output clock
Ideal for networking clocks
Operating voltage of 3V
Output enable mode tri-states outputs
Lead-free packaging available
Available in SOIC package
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
DESCRIPTION:
The 5V551 clock driver is built using advanced CMOS technology. This
lowskewclockdriveroffers1:4fanout. Thefanoutfromasingleinputreduces
loading on the preceding driver and provides an efficient clock distribution
network. The 5V551 offers low capacitance inputs. Typical applications are
clockandsignaldistribution.
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