參數(shù)資料
型號(hào)： ID8259A
廠商： Intel Corp.
英文描述： PROGRAMMABLE INTERRUPT CONTROLLER
中文描述： 可編程中斷控制器
文件頁(yè)數(shù)： 4/24頁(yè)
文件大小： 325K
代理商： ID8259A
8259A
The 8259A is a device specifically designed for use
in real time, interrupt driven microcomputer systems.
It manages eight levels or requests and has built-in
features for expandability to other 8259A’s (up to 64
levels). It is programmed by the system’s software
as an I/O peripheral. A selection of priority modes is
available to the programmer so that the manner in
which the requests are processed by the 8259A can
be configured to match his system requirements.
The priority modes can be changed or reconfigured
dynamically at any time during the main program.
This means that the complete interrupt structure can
be defined as required, based on the total system
environment.
INTERRUPT REQUEST REGISTER (IRR) AND
IN-SERVICE REGISTER (ISR)
The interrupts at the IR input lines are handled by
two registers in cascade, the Interrupt Request Reg-
ister (IRR) and the In-Service (ISR). The IRR is used
to store all the interrupt levels which are requesting
service; and the ISR is used to store all the interrupt
levels which are being serviced.
PRIORITY RESOLVER
This logic block determines the priorites of the bits
set in the IRR. The highest priority is selected and
strobed into the corresponding bit of the ISR during
INTA pulse.
INTERRUPT MASK REGISTER (IMR)
The IMR stores the bits which mask the interrupt
lines to be masked. The IMR operates on the IRR.
Masking of a higher priority input will not affect the
interrupt request lines of lower quality.
INT (INTERRUPT)
This output goes directly to the CPU interrupt input.
The V
OH
level on this line is designed to be fully
compatible with the 8080A, 8085A and 8086 input
levels.
INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vector-
ing information onto the data bus. The format of this
data depends on the system mode (
m
PM) of the
8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8-bit buffer is used to inter-
face the 8259A to the system Data Bus. Control
words
and
status
information
through the Data Bus Buffer.
are
transferred
READ/WRITE CONTROL LOGIC
The function of this block is to accept OUTput com-
mands from the CPU. It contains the Initialization
Command Word (ICW) registers and Operation
Command Word (OCW) registers which store the
various control formats for device operation. This
function block also allows the status of the 8259A to
be transferred onto the Data Bus.
CS (CHIP SELECT)
A LOW on this input enables the 8259A. No reading
or writing of the chip will occur unless the device is
selected.
WR (WRITE)
A LOW on this input enables the CPU to write con-
trol words (ICWs and OCWs) to the 8259A.
RD (READ)
A LOW on this input enables the 8259A to send the
status of the Interrupt Request Register (IRR), In
Service Register (ISR), the Interrupt Mask Register
(IMR), or the Interrupt level onto the Data Bus.
A
0
This input signal is used in conjunction with WR and
RD signals to write commands into the various com-
mand registers, as well as reading the various status
registers of the chip. This line can be tied directly to
one of the address lines.
4
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