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參數(shù)資料
| 型號： | ID8259A |
| 廠商： | Intel Corp. |
| 英文描述： | PROGRAMMABLE INTERRUPT CONTROLLER |
| 中文描述： | 可編程中斷控制器 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 325K |
| 代理商： | ID8259A |
8259A
231468–23
Figure 10. IR Triggering Timing Requirements
If LTIM
e
‘1’, an interrupt request will be recognized
by a ‘high’ level on IR Input, and there is no need for
an edge detection. The interrupt request must be
removed before the EOI command is issued or the
CPU interrupts is enabled to prevent a second inter-
rupt from occurring.
The priority cell diagram shows a conceptual circuit
of the level sensitive and edge sensitive input circuit-
ry of the 8259A. Be sure to note that the request
latch is a transparent D type latch.
In both the edge and level triggered modes the IR
inputs must remain high until after the falling edge of
the first INTA. If the IR input goes low before this
time a DEFAULT IR7 will occur when the CPU ac-
knowledges the interrupt. This can be a useful safe-
guard for detecting interrupts caused by spurious
noise glitches on the IR inputs. To implement this
feature the IR7 routine is used for ‘‘clean up’’ simply
executing a return instruction, thus ignoring the inter-
rupt. If IR7 is needed for other purposes a default
IR7 can still be detected by reading the ISR. A nor-
mal IR7 interrupt will set the corresponding ISR bit, a
default IR7 won’t. If a default IR7 routine occurs dur-
ing a normal IR7 routine, however, the ISR will re-
main set. In this case it is necessary to keep track of
whether or not the IR7 routine was previously en-
tered. If another IR7 occurs it is a default.
The Special Fully Nest Mode
This mode will be used in the case of a big system
where cascading is used, and the priority has to be
conserved within each slave. In this case the fully
nested mode will be programmed to the master (us-
ing ICW4). This mode is similar to the normal nested
mode with the following exceptions:
a. When an interrupt request from a certain slave is
in service this slave is not locked out from the
master’s priority logic and further interrupt re-
quests from higher priority IR’s within the slave
will be recognized by the master and will initiate
interrupts to the processor. (In the normal nested
mode a slave is masked out when its request is in
service and no higher requests from the same
slave can be serviced.)
b. When exiting the Interrupt Service routine the
software has to check whether the interrupt serv-
iced was the only one from that slave. This is
done by sending a non-specific End of Interrupt
(EOI) command to the slave and then reading its
In-Service register and checking for zero. If it is
empty, a non-specific EOI can be sent to the
master too. If not, no EOI should be sent.
Buffered Mode
When the 8259A is used in a large system where
bus driving buffers are required on the data bus and
the cascading mode is used, there exists the prob-
lem of enabling buffers.
The buffered mode will structure the 8259A to send
an enable signal on SP/EN to enable the buffers. In
this mode, whenever the 8259A’s data bus outputs
are enabled, the SP/EN output becomes active.
This modification forces the use of software pro-
gramming to determine whether the 8259A is a mas-
ter or a slave. Bit 3 in ICW4 programs the buffered
mode, and bit 2 in ICW4 determines whether it is a
master or a slave.
18
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