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參數(shù)資料
| 型號(hào)： | ID8259A |
| 廠商： | Intel Corp. |
| 英文描述： | PROGRAMMABLE INTERRUPT CONTROLLER |
| 中文描述： | 可編程中斷控制器 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 325K |
| 代理商： | ID8259A |
8259A
Operation Control Word 1 (OCW1)
OCW1 sets and clears the mask bits in the interrupt
Mask Register (IMR). M
7
–M
0
represent the eight
mask bits. M
e
1 indicates the channel is masked
(inhibited), M
e
0 indicates the channel is enabled.
Operation Control Word 2 (OCW2)
R, SL, EOIDThese three bits control the Rotate and
End of Interrupt modes and combinations of the two.
A chart of these combinations can be found on the
Operation Command Word Format.
L
2
, L
1
, L
0
DThese bits determine the interrupt level
acted upon when the SL bit is active.
231468–17
Figure 8. Operation Command Word Format
(Continued)
14
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