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參數資料
| 型號： | ICXO58CL |
| 英文描述： | AREA CCD IMAGE ARRAY |
| 中文描述： | 面陣CCD的圖像陣列 |
| 文件頁數： | 8/18頁 |
| 文件大?。?/td> | 203K |
| 代理商： | ICXO58CL |
– 8 –
ICX058CL
Clock Switching Characteristics
Note)
Because the horizontal final stage transfer clock LH
φ
1
is connected to the horizontal transfer clock H
φ
1
,
specifications will be the same as H
φ
1
.
Item
Readout clock
Vertical transfer
clock
Reset gate clock
Substrate clock
V
T
V
φ
1
, V
φ
2
,
V
φ
3
, V
φ
4
H
φ
1
, LH
φ
1
H
φ
2
H
φ
1
, LH
φ
1
H
φ
2
φ
RG
φ
SUB
2.3
18
21
11
1.5
2.5
24
26
5.38
13
1.8
19.5
19
26
24
5.38
51
0.5
10
10
0.01
0.01
3
17.5
15
0.5
15
0.5
10
10
0.01
0.01
3
250
17.5
15
0.5
μs
ns
ns
μs
ns
μs
During
readout
1
2
During
drain charge
Symbol
twh
Min. Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
twl
tr
tf
Unit
Remarks
1
When vertical transfer clock driver CXD1267AN is used.
2
tf
≥
tr – 2ns, and the cross-point voltage (V
CR
) for the H
φ
1
· LH
φ
1
rising side of the H
φ
1
· LH
φ
1
and H
φ
2
waveforms must be at least 2.5V.
H
t
During
imaging
During
parallel-serial
conversion
Item
Horizontal transfer clock
3
The overlap period for twh and twl of horizontal transfer clocks H
φ
1
· LH
φ
1
and H
φ
2
is two.
H
φ
1
· LH
φ
1
, H
φ
2
16
20
ns
3
Symbol
two
Min.
Typ.
Max.
Unit
Remarks
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr
twh
tf
φ
M
φ
M
2
V
φ
SUB
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