- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360790 > ICXO58CL AREA CCD IMAGE ARRAY PDF資料下載
參數(shù)資料
| 型號： | ICXO58CL |
| 英文描述： | AREA CCD IMAGE ARRAY |
| 中文描述： | 面陣CCD的圖像陣列 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 203K |
| 代理商： | ICXO58CL |
– 3 –
ICX058CL
Bias Conditions
Item
Output amplifier drain voltage
Output amplifier gate voltage
Output amplifier source
Substrate voltage adjustment range
Fluctuation range after substrate voltage adjustment
Reset gate clock voltage adjustment range
Fluctuation range after reset gate clock voltage
adjustment
Protective transistor bias
V
DD
V
GG
V
SS
V
SUB
V
SUB
V
RGL
V
RGL
V
L
14.55
3.8
9.0
–3
1.0
–3
15.0
4.2
15.45
4.65
18.5
+3
4.0
+3
V
V
V
%
V
%
±5%
1
1
,
6
Symbol
Min.
Typ.
Max.
Unit
Remarks
DC Characteristics
Item
Output amplifier drain current
Input current
Input current
I
DD
I
IN1
I
IN2
5
1
10
mA
μA
μA
3
4
Symbol
Min.
Typ.
Max.
Unit
Remarks
Grounded with
820
resistor
2
1
Indications of substrate voltage (V
SUB
) · reset gate clock voltage (V
RGL
) setting value.
The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image
sensor by a special code. Adjust substrate voltage (V
SUB
) and reset gate clock voltage (V
RGL
) to the
indicated voltage. Fluctuation range after adjustment is ±3%.
V
SUB
code one character indication
V
RGL
code one character indication
↑ ↑
V
RGL
code V
SUB
code
Code and optimal setting correspond to each other as follows.
1
V
RGL
code
Optimal setting
1.0 1.5 2.0 2.5 3.0 3.5 4.0
2
3
4
5
6
7
V
SUB
code
Optimal setting
9.0 9.5
10.0 10.5 11.0 11.5 12.012.5 13.0 13.5 14.0 14.5 15.015.5 16.0 16.5 17.0 17.5 18.018.5
E
f
G
h
J
K
L
m
N
P
Q
R
S
T
U
V
W
X
Y
Z
<Example> “5L”
→
V
RGL
= 3.0V
V
SUB
= 12.0V
2
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform.
3
1) Current to each pin when 18V is applied to V
DD
, V
OUT
, Vss and SUB pins, while pins that are not tested
are grounded.
2) Current to each pin when 20V is applied sequentially to V
φ
1
, V
φ
2
, V
φ
3
and V
φ
4
pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.
3) Current to each pin when 15V is applied sequentially to RG, LH
φ
1
, H
φ
1
, H
φ
2
and V
GG
pins, while pins
that are not tested are grounded. However, 15V is applied to SUB pin.
4) Current to V
L
pin when 30V is applied to V
φ
1
, V
φ
2
, V
φ
3
, V
φ
4
, V
DD
and V
OUT
pins or when, 24V is applied
to RG pin or when, 20V is applied to V
GG
, Vss, H
φ
1
, H
φ
2
and LH
φ
1
pins, while V
L
pin is grounded.
However, GND and SUB pins are left open.
4
Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ID1014 | White Bronze |
| ID1015 | Cable Stripping Process for SSMT Surface Mount Connector Series |
| ID101 | SCRs .5 Amp, Planar |
| ID101 | MONOLITHIC DUAL PICO AMPERE DIODES |
| ID1018 | Intermodulation in RF Coaxial Connectors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICY7C1357B-100BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| ICY7C1357C-100BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| ICY7C1362B-166BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| ICY7C1362C-166BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| ICY7C1362C-166BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。