參數(shù)資料
型號: ICSSSTV16857CG-T
英文描述: DDR 14-Bit Registered Buffer
中文描述: 復(fù)員14位注冊緩沖區(qū)
文件頁數(shù): 5/8頁
文件大?。?/td> 81K
代理商: ICSSSTV16857CG-T
5
CSSSTV16857C
0002F—10/25/02
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
From
(Input)
(Output)
MIN
200
1.7
TYP
MAX
f
max
t
PD
t
phl
MHz
ns
ns
CLK, CLK#
RESET#
Q
Q
2.1
2.5
3.5
SYMBOL
V
DD
= 2.5V ±0.2V
UNITS
To
Timing Requirements
1
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
200
2.5
3.5
4
f
clock
t
PD
t
RST
t
SL
Clock frequency
Clock to output time
Reset to output time
Output slew rate
Setup time, fast slew rate
2 & 4
Setup time, slow slew rate
3 & 4
Hold time, fast slew rate
2 & 4
Hold time, slow slew rate
3 & 4
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate
1V/ns.
3 - For data signal input slew rate
0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rates are
1V/ns.
MHz
ns
ns
V/ns
ns
ns
ns
ns
1.7
1
0.4
0.5
0.4
0.5
Notes:
UNITS
T
h
V
DDQ
= 2.5±0.2V
t
S
Data before CLK
, CLK#
Data after CLK
, CLK#
SYMBOL
PARAMETERS
相關(guān)PDF資料
PDF描述
ICSSSTV16857yG-T DDR 14-Bit Registered Buffer
ICSSSTV16859CG-T DDR 13-Bit to 26-Bit Registered Buffer
ICSSSTV16859yG-T DDR 13-Bit to 26-Bit Registered Buffer
ICSSSTV32852 DDR 24-Bit to 48-Bit Registered Buffer
ICSSSTV32852yHT DDR 24-Bit to 48-Bit Registered Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICSSSTV16857YG-T 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer
ICSSSTV16857YL-T 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer
ICSSSTV16859 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer
ICSSSTV16859CG-T 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer
ICSSSTV16859YG-T 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer