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參數(shù)資料
| 型號(hào)： | ICSSSTV16857CG-T |
| 英文描述： | DDR 14-Bit Registered Buffer |
| 中文描述： | 復(fù)員14位注冊(cè)緩沖區(qū) |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 81K |
| 代理商： | ICSSSTV16857CG-T |
4
CSSSTV16857C
0002F—10/25/02
Electrical Characteristics - DC
T
A
= 0 - 70o C; V
DD
= 2.5 +/-0.2V, V
DDQ
=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
V
IK
I
I
= -18mA
V
DDQ
2.3V
MIN
TYP
MAX
-1.2
UNITS
I
OH
= -100μA
2.3V-2.7V
V
DDQ
-
0.2
1.95
I
OH
= -16mA
I
OL
= 100μA
I
OL
= 16mA
V
I
= V
DD
or GND
RESET# = GND
V
I
= V
IH(AC)
or V
IL(AC)
,
RESET# = V
DD
RESET# = V
DD
,
V
I
= V
IH(AC)
or V
IL(AC)
,
CLK and CLK# switching
50% duty cycle.
RESET# = V
DD
,
V
I
= V
IH(AC)
or V
IL (AC)
,
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
I
OH
= -20mA
2.3V
2.3V-2.7V
2.3V
2.7V
0.2
0.35
±5
0.01
I
I
All Inputs
Standby (Static)
μA
μA
Operating (Static)
52
mA
Dynamic operating
(clock only)
75
μA/clock
MHz
Dynamic Operating
(per each data input)
15
μA/ clock
MHz/data
r
OH
r
OL
Output High
Output Low
[r
OH
-
r
OL
] each
separate bit
Data Inputs
CLK and CLK#
2.3V-2.7V
2.3V-2.7V
7
7
13.5
13
20
20
r
O(D)
2.5V
4
2.5
2.5
3.5
3.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
C
i
I
OL
= 20mA
I
O
= 20mA, T
A
= 25° C
V
OH
V
OL
I
DD
I
DDD
I
O
= 0
CONDITIONS
2.7V
2.5V
V
I
= V
REF
±350mV
V
ICR
= 1.25V, V
I(PP)
= 360mV
pF
V
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICSSSTV16857YG-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
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| ICSSSTV16859CG-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YG-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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