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參數資料
| 型號： | ICSSSTV16857CG-T |
| 英文描述： | DDR 14-Bit Registered Buffer |
| 中文描述： | 復員14位注冊緩沖區(qū) |
| 文件頁數： | 2/8頁 |
| 文件大?。?/td> | 81K |
| 代理商： | ICSSSTV16857CG-T |
2
CSSSTV16857C
0002F—10/25/02
General Description
The 14-bit ICSSSTV16857C is a universal bus driver designed for 2.3V to 2.7V V
DD
operation and SSTL_2 I/O levels,
except for the LVCMOS RESET# input.
Pin Configuration
R
1
,
E
B
,
1
,
1
1
,
2
,
1
4
,
3
,
1
,
1
,
2
,
2
,
4
,
3
,
4
,
4
3
3
,
3
,
2
3
3
M
U
,
2
,
1
,
,
,
2
,
N
N
,
2
,
1
,
,
I
P
E
M
A
N
N
I
P
E
P
Y
T
N
O
I
P
I
R
C
S
E
D
,
,
2
,
1
)
1
Q
T
U
P
T
U
O
t
p
o
a
D
,
6
D
N
G
R
W
P
d
n
u
o
G
1
,
3
,
4
8
2
,
,
2
,
3
Q
D
D
V
R
W
P
e
g
a
v
y
p
u
s
t
p
O
,
3
,
4
,
4
8
9
4
4
5
4
)
1
D
T
U
P
N
I
t
p
n
a
D
K
K
D
D
E
S
E
R
L
L
C
C
V
E
V
T
T
U
U
R
U
U
P
P
W
P
P
N
N
P
N
N
I
I
t
p
p
n
a
v
w
o
e
e
c
n
n
k
c
k
c
o
o
e
y
p
u
v
a
e
e
v
o
P
g
e
N
e
C
s
e
R
t
p
n
#
t
e
g
)
a
v
v
s
t
5
#
T
F
R
T
T
I
I
e
g
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge
of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an
LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16857C supports low-power
standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic
“Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always
be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic
“Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable the
differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until the
input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
相關PDF資料 |
PDF描述 |
|---|---|
| ICSSSTV16857yG-T | DDR 14-Bit Registered Buffer |
| ICSSSTV16859CG-T | DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859yG-T | DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV32852 | DDR 24-Bit to 48-Bit Registered Buffer |
| ICSSSTV32852yHT | DDR 24-Bit to 48-Bit Registered Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ICSSSTV16857YG-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16857YL-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16859 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859CG-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YG-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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