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參數(shù)資料
| 型號(hào)： | ICSSSTUB32864Az(LF)T |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 25-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 25位可配置的注冊(cè)緩沖DDR2內(nèi)存 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | ICSSSTUB32864AZ(LF)T |
ICSSSTUB32864A
Advance Information
1166—10/05/05
10
Notes: 1. C
L
includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR
≤
10MHz, Z
O
=
50
, input slew rate = 1 V/ns ±20% (unless otherwise specified).
Figure 7 — Output Slew-Rate
(V
DD
= 1.8V ± 0.1V)
C
L
= 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Test Point
DUT
Out
dt_f
V
OL
V
OH
VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT
80%
Output
20%
dv_f
R
L
= 50
C
L
= 10 pF
(see Note 1)
LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT
Test Point
DUT
Out
dt_r
V
OL
V
OH
VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT
80%
Output
20%
dv_r
R
L
= 50
V
DD
Measurement Information
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